cibyr / lefdef

Related projects: ⓘ

• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆26Updated 5 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆50Updated 4 years ago
• bkoppelmann / lefdef-toolkit
  Source code for LEF/DEF
  ☆11Updated 5 years ago
• parallaxsw / OpenSTA
  ☆35Updated last week
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆50Updated 2 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆64Updated 6 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆52Updated 7 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆79Updated 3 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆101Updated 3 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆79Updated 2 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆29Updated 4 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆140Updated 11 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 4 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆37Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆38Updated 4 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆53Updated 3 months ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆118Updated last year
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆120Updated 2 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆72Updated this week
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆13Updated 6 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆44Updated 2 months ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆20Updated 5 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆25Updated 2 years ago
• pkuzjx / eda-collection
  ☆95Updated 4 years ago