Alternatives and similar repositories for OpenVAF

Users that are interested in OpenVAF are comparing it to the libraries listed below

• dwarning / VA-Models
  Verilog-A simulation models
  ☆86Updated 3 weeks ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆73Updated last month
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆50Updated 9 months ago
• OpenVAF / OpenVAF-Reloaded
  OpenVAF revived by community
  ☆17Updated 3 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆206Updated this week
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆88Updated 7 months ago
• arpadbuermen / OpenVAF
  An innovative Verilog-A compiler
  ☆31Updated last month
• efabless / mpw_precheck
  ☆43Updated 8 months ago
• dan-fritchman / Layout21
  Integrated Circuit Layout
  ☆57Updated 8 months ago
• efabless / caravel_user_project_analog
  ☆50Updated 9 months ago
• google / bigspicy
  ☆40Updated 2 years ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆319Updated 8 months ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆173Updated last week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆298Updated 3 weeks ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆40Updated 3 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆120Updated last week
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆36Updated 6 months ago
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆50Updated last week
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆49Updated 2 months ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆125Updated last week
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 9 months ago
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆102Updated 2 years ago
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• mineda-support / ICPS2023_5
  ☆57Updated 4 months ago
• google / sky90fd-pdk
  ☆121Updated 2 years ago
• efabless / chipignite-resources
  ☆84Updated 3 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆170Updated this week
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆117Updated 4 years ago
• iic-jku / analog-circuit-design
  Course material for a basic hands-on analog circuit design course with IC emphasis
  ☆161Updated 2 weeks ago