pascalkuthe / OpenVAF
An innovative Verilog-A compiler
☆149Updated 8 months ago
Alternatives and similar repositories for OpenVAF:
Users that are interested in OpenVAF are comparing it to the libraries listed below
- Verilog-A simulation models☆71Updated 3 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆273Updated 3 weeks ago
- ☆38Updated 2 months ago
- ☆111Updated last year
- Hardware Description Library☆78Updated 3 weeks ago
- Course material for a basic hands-on analog circuit design course with IC emphasis☆110Updated last week
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆42Updated 10 months ago
- ☆45Updated 3 months ago
- Circuit Automatic Characterization Engine☆46Updated 3 months ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆116Updated 3 weeks ago
- ☆79Updated 2 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆42Updated last week
- Coriolis VLSI EDA Tool (LIP6)☆65Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 3 months ago
- ☆142Updated 3 years ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆95Updated 2 weeks ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆177Updated last week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆322Updated this week
- Fabric generator and CAD tools☆178Updated 3 weeks ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆112Updated 3 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆208Updated 6 months ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆153Updated last month
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆378Updated this week
- ☆41Updated 2 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆282Updated 2 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆62Updated last month
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 7 years ago
- Qrouter detail router for digital ASIC designs☆57Updated 3 weeks ago
- ☆54Updated last year
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆27Updated last week