Alternatives and similar repositories for OpenVAF

Users that are interested in OpenVAF are comparing it to the libraries listed below

• dwarning / VA-Models
  Verilog-A simulation models
  ☆78Updated last week
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆50Updated 6 months ago
• efabless / caravel_user_project_analog
  ☆48Updated 6 months ago
• arpadbuermen / OpenVAF
  An innovative Verilog-A compiler
  ☆28Updated 2 months ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆45Updated 3 weeks ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆82Updated 4 months ago
• google / bigspicy
  ☆41Updated 2 years ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆306Updated 5 months ago
• OpenVAF / OpenVAF-Reloaded
  OpenVAF revived by community
  ☆13Updated 2 weeks ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated 2 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆192Updated last week
• iic-jku / analog-circuit-design
  Course material for a basic hands-on analog circuit design course with IC emphasis
  ☆133Updated last week
• efabless / chipignite-resources
  ☆81Updated 2 years ago
• efabless / mpw_precheck
  ☆42Updated 5 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆35Updated last week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆287Updated last month
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆69Updated last week
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆31Updated last week
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 6 months ago
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆37Updated last year
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆121Updated 2 months ago
• dan-fritchman / Layout21
  Integrated Circuit Layout
  ☆54Updated 5 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆112Updated this week
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• bmurmann / EE628
  EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
  ☆162Updated last week
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• mabrains / caravel_analog_rf
  Analog and RF blocks on Skywaters 130nm
  ☆11Updated 3 years ago
• efabless / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆68Updated last week
• dreoilin / pygmid
  A python3 gm/ID starter kit
  ☆51Updated 11 months ago