yuchsiao / caplet

Related projects: ⓘ

• bluecheetah / cbag
  A C++ VLSI circuit schematic and layout database library
  ☆13Updated 2 months ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆28Updated 4 years ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆21Updated last year
• aolofsson / IDEA
  ☆28Updated 4 years ago
• The-OpenROAD-Project / OpenRCX
  ☆17Updated 3 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆37Updated 5 years ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆29Updated last year
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 3 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆49Updated 3 weeks ago
• cogenda / VA-BSIM48
  Verilog-A implementation of MOSFET model BSIM4.8
  ☆10Updated 4 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆21Updated last year
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆36Updated 5 months ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆27Updated last month
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆37Updated last year
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆24Updated 2 years ago
• RIOSMPW / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆38Updated 4 months ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆15Updated 4 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆50Updated 2 years ago
• analogdevicesinc / vampyre
  ☆16Updated 5 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last month
• ABKGroup / PROBE3.0
  ☆34Updated 5 months ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆16Updated 9 months ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆19Updated 2 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆20Updated 5 years ago
• christophmuellerorg / spectre_python
  Simple and most probably incomplete parser for spectre netlists
  ☆16Updated 7 years ago
• laurentc2 / FreePDK45_for_KLayout
  KLayout technology files for FreePDK45
  ☆20Updated 3 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆27Updated 9 years ago
• google / bigspicy
  ☆36Updated last year
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆22Updated last year
• aolofsson / POSH
  ☆37Updated 4 years ago