GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.
☆26Jul 1, 2024Updated 2 years ago
Alternatives and similar repositories for caplet
Users that are interested in caplet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Parasitic Extraction for KLayout☆45Jun 8, 2026Updated 3 weeks ago
- FastCap is the premium capacitance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastCap …☆54Nov 26, 2015Updated 10 years ago
- FasterCap is a powerful three- and two-dimensional capactiance extraction program.☆38Oct 25, 2019Updated 6 years ago
- ☆12Nov 18, 2024Updated last year
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆18Mar 28, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆21Oct 28, 2024Updated last year
- ☆14Jul 19, 2024Updated last year
- KLayout technology files for FreePDK45☆25Jun 12, 2021Updated 5 years ago
- ☆28Dec 16, 2020Updated 5 years ago
- An EDA tool for automatic device sizing using Gm/Id method.☆16Jan 10, 2026Updated 5 months ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆26May 22, 2022Updated 4 years ago
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 4 years ago
- Cornerstone PDK☆22Jun 24, 2026Updated last week
- Kicad 5.x symbol and footprint libraries for the open smartwatch☆16Feb 18, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆86Oct 29, 2025Updated 8 months ago
- Primitives for GF180MCU provided by GlobalFoundries.☆57Aug 28, 2023Updated 2 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆133Apr 23, 2023Updated 3 years ago
- Interchange formats for chip design.☆39Feb 15, 2026Updated 4 months ago
- ☆33May 11, 2026Updated last month
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆25Feb 24, 2026Updated 4 months ago
- Python interface for Cadence Spectre☆28Feb 17, 2026Updated 4 months ago
- Android SDK for ActiveLook eyewear☆15May 5, 2026Updated last month
- This project is dedicated to building an ElectroMagnetic workbench for FreeCAD. FreeCAD is a free 3D parametric CAD. FreeCAD is used as p…☆68Apr 12, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This library is a low level parser for the GDSII file format.☆35Jun 25, 2017Updated 9 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆31Oct 28, 2024Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- ☆21Updated this week
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆15Sep 3, 2018Updated 7 years ago
- Reads a Cadence techfile into KLayout and produces layer properties from it☆31Oct 22, 2023Updated 2 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆19Dec 5, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- tools regarding on analog modeling, validation, and generation☆24Apr 11, 2023Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆46Dec 5, 2017Updated 8 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Open source designs developed with the IHP 130nm BiCMOS Open PDK in the FMD_QNC project. Documentation at https://ihp-open-designlib.read…☆70Jun 5, 2026Updated 3 weeks ago
- Custom IC Creator Simulation tools☆28Jun 22, 2026Updated last week