Alternatives and similar repositories for Layout21

Users that are interested in Layout21 are comparing it to the libraries listed below

• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆32Updated 4 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆82Updated 5 months ago
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆164Updated last year
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆37Updated last month
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 8 months ago
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆43Updated this week
• google / bigspicy
  ☆41Updated 2 years ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆34Updated last week
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆102Updated 7 months ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_pr
  Primitives for GF180MCU provided by GlobalFoundries.
  ☆51Updated 2 years ago
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆57Updated 5 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆54Updated last month
• dwarning / VA-Models
  Verilog-A simulation models
  ☆79Updated last month
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆35Updated 2 years ago
• efabless / caravel_user_project_analog
  ☆49Updated 7 months ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆51Updated 7 months ago
• idea-fasoc / fasoc
  ☆55Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 11 months ago
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆37Updated last year
• TinyTapeout / xschem-viewer
  Online viewer of Xschem schematic files
  ☆27Updated 9 months ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆40Updated 2 years ago
• arpadbuermen / OpenVAF
  An innovative Verilog-A compiler
  ☆28Updated this week
• Xyce / XDM
  This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
  ☆20Updated last year
• mbalestrini / tinytapeout_gds_viewer
  ☆17Updated last month
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆48Updated last week