Alternatives and similar repositories for Layout21:

Users that are interested in Layout21 are comparing it to the libraries listed below

• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆29Updated this week
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆79Updated last month
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆29Updated this week
• google / bigspicy
  ☆39Updated last year
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆32Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 8 months ago
• gdsfactory / skywater130
  skywater 130nm pdk
  ☆27Updated last week
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆26Updated 3 weeks ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated last week
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago
• Vlsir / Hdl21Schematics
  Hdl21 Schematics
  ☆14Updated last year
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 7 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 2 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆51Updated 11 months ago
• Xyce / XDM
  This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
  ☆19Updated last year
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆52Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 5 months ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆37Updated 2 years ago
• pascalkuthe / OpenVAF
  An innovative Verilog-A compiler
  ☆143Updated 7 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆43Updated 6 months ago
• idea-fasoc / fasoc
  ☆53Updated last year
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆39Updated last year
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆100Updated 2 months ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆65Updated 2 months ago
• Ravenslofty / librecell
  ☆21Updated 3 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆26Updated 2 years ago
• dan-fritchman / Spice21
  SPICE for the 21st Century
  ☆29Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago