Alternatives and similar repositories for Quine-McCluskey

Users that are interested in Quine-McCluskey are comparing it to the libraries listed below

• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• amahzoon / genmul
  ☆18Updated 4 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆38Updated last year
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 5 months ago
• yaohsiaopid / rtl2uspec
  ☆11Updated 4 months ago
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 6 years ago
• ckchengucsd / SMTCellUCSD
  Cell Layout Generation for DTCO/STCO Exploration Toolkit
  ☆21Updated 5 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 years ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆33Updated last year
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 7 months ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 4 months ago
• icgrp / hipr
  ☆16Updated 2 years ago
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆14Updated 7 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆32Updated 7 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• iscas-tis / CHA
  ☆19Updated last year
• hadarshavit / revisiting_satzilla
  SATZilla SAT feature extraction tool
  ☆11Updated last year
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 6 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated 2 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated last week
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 2 months ago