Alternatives and similar repositories for ysyx-slides

Users that are interested in ysyx-slides are comparing it to the libraries listed below

• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆23Updated last year
• puckbee / moli
  ☆32Updated 2 months ago
• OSCPU / yosys-sta
  ☆83Updated 5 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆179Updated 11 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 7 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 5 months ago
• OSCPU / ysyx-workbench
  ☆156Updated last week
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆32Updated last week
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆161Updated 8 months ago
• YSYX-OpenDoc / riscv-isa-manual
  ☆20Updated 4 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 6 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆20Updated last month
• OSCPU / ysyxSoC
  ☆87Updated last week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 6 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆11Updated 11 months ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆16Updated last year
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆40Updated 5 years ago
• OSCPU / chisel-playground
  ☆67Updated 8 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆25Updated 10 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆157Updated this week
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆40Updated last year
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Out-of-order CPU design from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品
  ☆20Updated last year
• iFuProcessor / iFuCore
  ☆20Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆70Updated last week
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆61Updated last year
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 9 months ago