Undergraduate digital circuit laboratory
☆29Jan 4, 2024Updated 2 years ago
Alternatives and similar repositories for veriloglabs
Users that are interested in veriloglabs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Reed Solomon Encoder and Decoder Digital IP☆22Jun 14, 2020Updated 5 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- Source code for Zynq OLED controller☆16Oct 11, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆23Dec 17, 2019Updated 6 years ago
- A Verilog implementation of a processor cache.☆39Dec 29, 2017Updated 8 years ago
- verilog☆21Jun 26, 2023Updated 2 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- implementation of opencv sgbm(disparity map extract) on FPGA☆12Oct 27, 2021Updated 4 years ago
- It is a fpga implementation of an i2c master, framebuffer for sdd1306 display☆11May 14, 2021Updated 5 years ago
- This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog…☆40Mar 1, 2023Updated 3 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Mar 16, 2023Updated 3 years ago
- 基于STM32F407实现2023年电赛H题，使用到的模块有SI5351时钟模块，两块AD9833，一块AD630，增益偏置调整电路若干☆13Jan 17, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- Video Stream Scaler☆42Jul 17, 2014Updated 11 years ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- A Verilog implementation of the popular video game Tetris.☆27Oct 28, 2015Updated 10 years ago
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 7 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- Tutorial☆15Jun 13, 2020Updated 5 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Reed Solomon Decoder (204,188)☆13Jul 17, 2014Updated 11 years ago
- asynchronous fifo based on verilog☆16Apr 14, 2022Updated 4 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- 基于ESP32开发的便携式T12电烙铁焊笔 ，拥有PD100W诱骗，OLED显示， 温度可调，姿态唤醒，多功能设置，断电存储，自动休眠，OTA等功能☆13May 4, 2023Updated 3 years ago
- 七路图像在FPGA中实现拼接，代码会不断添加进来。☆29Aug 17, 2021Updated 4 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated last year
- Forces DeepSeek R1 models to engage in extended reasoning by intercepting early termination tokens.☆19Feb 12, 2025Updated last year
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Accelerating DNN inference and training on Zynq☆16Jul 22, 2020Updated 5 years ago
- 一个SpringBoot可以使用的配置中心☆11Aug 3, 2023Updated 2 years ago
- 通过Nacos实现动态线程池技术，并且使用xxl-job实现消息通知功能。☆14Jun 16, 2023Updated 2 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019☆12Jun 7, 2019Updated 6 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago