Undergraduate digital circuit laboratory
☆29Jan 4, 2024Updated 2 years ago
Alternatives and similar repositories for veriloglabs
Users that are interested in veriloglabs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Reed Solomon Encoder and Decoder Digital IP☆22Jun 14, 2020Updated 6 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆16Oct 1, 2019Updated 7 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- ☆31Aug 8, 2020Updated 6 years ago
- Source code for Zynq OLED controller☆16Oct 11, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- verilog☆21Jun 26, 2023Updated 3 years ago
- ☆12Feb 22, 2024Updated 2 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆27Dec 17, 2019Updated 6 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆29Mar 11, 2022Updated 4 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- SJTU MST3314 course project (CNN). A binary classification convolutional neural network in Verilog.☆15Mar 8, 2026Updated 7 months ago
- CNN Accelerator for Zynq☆13Dec 27, 2019Updated 6 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 10 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- It is a fpga implementation of an i2c master, framebuffer for sdd1306 display☆12May 14, 2021Updated 5 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆24Mar 16, 2023Updated 3 years ago
- ☆12Dec 15, 2023Updated 2 years ago
- This is a SystemVerilog HDL implementation of Karatsuba multiplier.☆11Jul 8, 2020Updated 6 years ago
- This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog…☆40Mar 1, 2023Updated 3 years ago
- Video Stream Scaler☆43Jul 17, 2014Updated 12 years ago
- implementation of opencv sgbm(disparity map extract) on FPGA☆14Oct 27, 2021Updated 5 years ago
- ☆13May 13, 2021Updated 5 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 8 years ago
- A Verilog implementation of the popular video game Tetris.☆28Oct 28, 2015Updated 11 years ago
- 哈工大2023处理器设计与计算机体系结构实验☆27Sep 3, 2024Updated 2 years ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆30Aug 17, 2021Updated 5 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- The Verilog model for SRAM IS61WV102416 chip with timings☆10Mar 14, 2015Updated 11 years ago
- ☆18Apr 7, 2022Updated 4 years ago
- Open-source NPU (Neural Processing Unit) for LLM inference - runs GPT-2, LLaMA, Mistral, Qwen2☆12Mar 15, 2026Updated 7 months ago
- Tutorial☆16Jun 13, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog implementation of the SHA-1 cryptgraphic hash function☆57Apr 3, 2025Updated last year
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 4 years ago
- Forces DeepSeek R1 models to engage in extended reasoning by intercepting early termination tokens.☆19Feb 12, 2025Updated last year
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated 2 years ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Accelerating DNN inference and training on Zynq☆16Jul 22, 2020Updated 6 years ago