Xinyang-ZHANG / MNISTLinks
MNIST using tensorflow, c++ and fpga (zynq7010)
☆25Updated 2 years ago
Alternatives and similar repositories for MNIST
Users that are interested in MNIST are comparing it to the libraries listed below
Sorting:
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆183Updated 8 months ago
- Convolutional Neural Network RTL-level Design☆59Updated 3 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆114Updated last year
- fpga跑sobel识别算法☆36Updated 4 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆156Updated 2 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆56Updated 4 months ago
- Nuclei E203 with yolo accelerator based on xc7k325☆14Updated 11 months ago
- some interesting demos for starters☆81Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆121Updated 2 months ago
- 帧差法运动目标检测,基于ZYNQ7020☆68Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆41Updated 2 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- ☆242Updated last year
- 2023集创赛紫光同创杯一等奖项目☆119Updated last year
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆77Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆183Updated last year
- 一个开源的FPGA神经网络加速器。☆169Updated last year
- FPGA实现简单的图像处理算法☆47Updated 2 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆150Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- ☆10Updated 3 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆80Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- FPGA project☆222Updated 3 years ago
- AXI总线连接器☆100Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆50Updated 11 months ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago