vortexgpgpu / pocl
a clone of POCL that includes RISC-V newlib devices support and Vortex
☆37Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for pocl
- ☆30Updated 4 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated 4 months ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆85Updated last year
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆42Updated 3 years ago
- The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.☆33Updated 3 years ago
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆17Updated 8 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆37Updated 3 weeks ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- An optimized neural network operator library for chips base on Xuantie CPU.☆86Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆33Updated 2 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆35Updated last week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆148Updated 9 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆88Updated last week
- ☆75Updated 2 years ago
- Simple demonstration of using the RISC-V Vector extension☆37Updated 7 months ago
- Unit tests generator for RVV 1.0☆63Updated last month
- ☆42Updated 3 years ago
- ⛔ DEPRECATED ⛔ HERO Software Development Kit☆20Updated 2 years ago
- Extremely Simple Microbenchmarks☆30Updated 6 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆109Updated 3 weeks ago
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- Learn NVDLA by SOMNIA☆26Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- ☆36Updated 2 weeks ago