vortexgpgpu / poclLinks
a clone of POCL that includes RISC-V newlib devices support and Vortex
☆42Updated 3 months ago
Alternatives and similar repositories for pocl
Users that are interested in pocl are comparing it to the libraries listed below
Sorting:
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated last year
- The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.☆40Updated 3 years ago
- ☆35Updated last year
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆22Updated 4 years ago
- Example for running IREE in a bare-metal Arm environment.☆36Updated 4 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆106Updated 2 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆35Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆90Updated last year
- A repository that compliments gpgpu-sim, providing automated regression scripts, simulation launching utilities and the code + arguments …☆74Updated 4 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆36Updated last week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆118Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆103Updated 2 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- Vortex Graphics☆79Updated 9 months ago
- Simple demonstration of using the RISC-V Vector extension☆45Updated last year
- ☆68Updated last week
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆35Updated last month
- ☆62Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 3 weeks ago
- RISC-V GPGPU☆34Updated 5 years ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆64Updated 11 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last month
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆35Updated this week