vortexgpgpu / pocl
a clone of POCL that includes RISC-V newlib devices support and Vortex
☆38Updated 7 months ago
Alternatives and similar repositories for pocl:
Users that are interested in pocl are comparing it to the libraries listed below
- ☆33Updated 6 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 4 years ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated 7 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- LLVM OpenCL C compiler suite for ventus GPGPU☆40Updated last week
- Ventus GPGPU ISA Simulator Based on Spike☆39Updated 2 weeks ago
- The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.☆36Updated 3 years ago
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆88Updated last year
- Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…☆46Updated 5 months ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆30Updated last year
- Learn NVDLA by SOMNIA☆30Updated 5 years ago
- ☆41Updated this week
- ☆42Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- ☆16Updated 6 months ago
- ☆42Updated 5 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆34Updated 5 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆148Updated last year
- gem5 simulator with a gpgpu+graphics GPU model☆52Updated 4 years ago
- Extremely Simple Microbenchmarks☆30Updated 6 years ago
- ☆89Updated 11 months ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated 4 months ago
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Updated 8 years ago
- Floating point modules for CHISEL☆31Updated 10 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆97Updated 3 weeks ago