ZipCPU / wbspi
A collection of SPI related cores
☆17Updated 5 months ago
Alternatives and similar repositories for wbspi:
Users that are interested in wbspi are comparing it to the libraries listed below
- Wishbone interconnect utilities☆39Updated 2 months ago
- Universal Advanced JTAG Debug Interface☆17Updated 11 months ago
- ☆16Updated 5 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 2 months ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- simple hyperram controller☆11Updated 6 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- SGMII☆12Updated 10 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- A padring generator for ASICs☆25Updated last year
- ☆13Updated last month
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- ☆10Updated last year
- RISC-V processor☆29Updated 2 years ago
- SystemC to Verilog Synthesizable Subset Translator☆9Updated last year
- SystemVerilog Logger☆17Updated 2 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 weeks ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 4 months ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated last week
- Fusesoc compatible rtl cores☆15Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- USB virtual model in C++ for Verilog☆29Updated 6 months ago