ZipCPU / wbspi
A collection of SPI related cores
☆15Updated 2 months ago
Alternatives and similar repositories for wbspi:
Users that are interested in wbspi are comparing it to the libraries listed below
- Wishbone interconnect utilities☆38Updated 8 months ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Universal Advanced JTAG Debug Interface☆17Updated 8 months ago
- A padring generator for ASICs☆24Updated last year
- SGMII☆10Updated 10 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆21Updated 3 months ago
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆15Updated 2 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- USB virtual model in C++ for Verilog☆29Updated 3 months ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 6 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- ☆59Updated 3 years ago
- SystemVerilog Logger☆17Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- RISC-V processor☆28Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- Extensible FPGA control platform☆56Updated last year
- Master-thesis-final☆18Updated last year
- SystemC to Verilog Synthesizable Subset Translator☆9Updated last year