snbk001 / Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
☆101Updated last year
Alternatives and similar repositories for Verilog-Design-Examples:
Users that are interested in Verilog-Design-Examples are comparing it to the libraries listed below
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆140Updated 5 months ago
- ☆107Updated last year
- Architectural design of data router in verilog☆28Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆63Updated last year
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆115Updated 3 years ago
- UVM and System Verilog Manuals☆39Updated 5 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆32Updated last year
- ☆38Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- Single Cycle RISC MIPS Processor☆31Updated 3 years ago
- ☆16Updated last year
- opensource EDA tool flor VLSI design☆31Updated last year
- This is a detailed SystemVerilog course☆80Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆89Updated 2 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆13Updated last year
- ☆12Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆9Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- ☆22Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆69Updated 2 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆34Updated 5 years ago
- ☆130Updated 2 years ago
- ☆11Updated this week
- Verilog HDL files☆118Updated 8 months ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆80Updated last year
- ☆16Updated last year