snbk001 / Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
☆120Updated last year
Alternatives and similar repositories for Verilog-Design-Examples:
Users that are interested in Verilog-Design-Examples are comparing it to the libraries listed below
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- ☆109Updated last year
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆120Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- ☆154Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆143Updated 2 weeks ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- UVM and System Verilog Manuals☆41Updated 6 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- VIP for AXI Protocol☆131Updated 2 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆148Updated 10 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆40Updated last year
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- Implementation of CNN using Verilog☆212Updated 7 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- ☆43Updated 3 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆101Updated 3 months ago
- This is a detailed SystemVerilog course☆96Updated last month
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆95Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆84Updated 5 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆101Updated 11 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆201Updated last year
- ☆22Updated last year
- A verilog based 5-stage pipelined RISC-V Processor code.☆23Updated 5 years ago
- Basic RISC-V Test SoC☆121Updated 6 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year