Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
☆210Jan 29, 2024Updated 2 years ago
Alternatives and similar repositories for Verilog-Design-Examples
Users that are interested in Verilog-Design-Examples are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆20Aug 6, 2025Updated last year
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- DDR2 memory controller written in Verilog☆84Feb 28, 2012Updated 14 years ago
- 30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills a…☆73Sep 30, 2023Updated 2 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆156Jul 17, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- APB master and slave developed in RTL.☆27Oct 25, 2025Updated 9 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆124Jul 9, 2023Updated 3 years ago
- Basic RISC-V Test SoC☆206Apr 7, 2019Updated 7 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆39Oct 29, 2023Updated 2 years ago
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆67Nov 25, 2020Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆40Nov 6, 2022Updated 3 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆146Apr 3, 2020Updated 6 years ago
- A place to keep my synthesizable verilog examples.☆58May 19, 2026Updated 2 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆82Oct 7, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is a detailed SystemVerilog course☆166Mar 4, 2025Updated last year
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆144Jul 31, 2022Updated 4 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- ☆56Jun 19, 2021Updated 5 years ago
- Verilog for ASIC Design☆35Sep 13, 2021Updated 4 years ago
- Router 1x3 design and uvm verification testbach and coverage report☆14Nov 8, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog Project☆22Aug 30, 2021Updated 4 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- Parametric AXI4 crossbar in SystemVerilog☆240May 25, 2026Updated 2 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆471Feb 13, 2026Updated 5 months ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆71Feb 18, 2024Updated 2 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 7 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 7 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆51Dec 3, 2023Updated 2 years ago
- Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024☆25Mar 20, 2025Updated last year
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆43Dec 5, 2019Updated 6 years ago
- Structured UVM Course☆76Jan 4, 2024Updated 2 years ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 11 months ago
- AMBA bus lecture material☆547Jan 21, 2020Updated 6 years ago