adki / gen_ambaLinks
AMBA bus generator including AXI, AHB, and APB
☆105Updated 3 years ago
Alternatives and similar repositories for gen_amba
Users that are interested in gen_amba are comparing it to the libraries listed below
Sorting:
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- AHB3-Lite Interconnect☆89Updated last year
- AXI DMA 32 / 64 bits☆115Updated 10 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆208Updated last year
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- ☆67Updated 9 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- An AXI4 crossbar implementation in SystemVerilog☆161Updated 3 weeks ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆121Updated 7 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- amba3 apb/axi vip☆50Updated 10 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- UVM AHB VIP☆86Updated 7 months ago
- UVM examples and projects☆140Updated 2 weeks ago
- SystemVerilog VIP for AMBA APB protocol☆76Updated 3 years ago
- round robin arbiter☆74Updated 10 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- AXI总线连接器☆100Updated 5 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆144Updated 6 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆101Updated 7 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆105Updated 6 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆168Updated 7 months ago