FPGA based microcomputer sandbox for software and RTL experimentation
☆77Updated this week
Alternatives and similar repositories for boxlambda
Users that are interested in boxlambda are comparing it to the libraries listed below
Sorting:
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆29Jun 12, 2019Updated 6 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- There are many RISC V projects on iCE40. This one is mine.☆14Jun 25, 2020Updated 5 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Apr 22, 2024Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆27Jan 6, 2023Updated 3 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆23Nov 15, 2018Updated 7 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- LiteX-based gateware for LimeSDR boards.☆19Updated this week
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- RISC-V CSR Access Routines☆15Dec 27, 2022Updated 3 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- RISC-V Nox core☆71Jul 22, 2025Updated 7 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Aug 27, 2024Updated last year
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 4 years ago
- Opensource DDR3 Controller☆418Jan 18, 2026Updated last month
- FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)☆23Jan 15, 2022Updated 4 years ago
- a USB2 highspeed device core, written in amaranth HDL☆52Sep 17, 2024Updated last year
- RISC-V RV32IMAFC Core for MCU☆42Feb 1, 2025Updated last year
- Utilities for the ECP5 FPGA☆17Aug 5, 2021Updated 4 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- KiCad symbol library for sky130 and gf180mcu PDKs☆34Feb 14, 2024Updated 2 years ago
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆38Jan 11, 2023Updated 3 years ago
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago
- VHDL implementation of an AVR processor.☆19Apr 7, 2015Updated 10 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- YM2151 clone in verilog. FPGA proven.☆85Jan 6, 2025Updated last year
- Amaranth HDL libary for building USB-capable SoC designs.☆27Oct 31, 2025Updated 4 months ago
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 3 years ago
- LiteX based FPGA gateware for Thunderscope.☆28Feb 14, 2026Updated 2 weeks ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆43Apr 11, 2024Updated last year
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆224Feb 19, 2026Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Feb 3, 2026Updated 3 weeks ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆26Feb 13, 2026Updated 2 weeks ago
- ZPUino HDL implementation☆91Aug 6, 2018Updated 7 years ago