An FPGA-based RISC-V CPU
☆16Dec 7, 2021Updated 4 years ago
Alternatives and similar repositories for riscv
Users that are interested in riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 5 stage pipeline, single cycle risc-V implementation☆32Mar 9, 2024Updated 2 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- A 5 stage-pipeline RV32I implementation in VHDL☆23Mar 13, 2020Updated 6 years ago
- ☆12Jun 22, 2020Updated 5 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆21Jun 3, 2023Updated 2 years ago
- RISC-V Rocket on the Digilent Zybo Board☆21Aug 6, 2014Updated 11 years ago
- Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology☆25Jul 23, 2022Updated 3 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆109Nov 14, 2018Updated 7 years ago
- Implementation of algorithms for refinement of direction of arrival estimators by optimization☆15Jun 2, 2021Updated 4 years ago
- This thesis applies an autoencoder deep neural network to the multichannel speech enhancement problem. It takes the problem from dataset …☆13Sep 1, 2022Updated 3 years ago
- 32-bit soft RISCV processor for FPGA applications☆19Nov 25, 2023Updated 2 years ago
- ☆11Jan 14, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contains getting started projects related to all PSoC4 pioneer kits.☆14Oct 30, 2018Updated 7 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 4 years ago
- ☆15Feb 27, 2024Updated 2 years ago
- Mini RISC-V SOC☆12Nov 13, 2015Updated 10 years ago
- asynchronous fifo based on verilog☆16Apr 14, 2022Updated 4 years ago
- ☆23Jun 23, 2024Updated last year
- 基于物联网 技术以及人脸识别技术，系统底层采用ESP32开发板为核心，在ESP32开发板上接入了红外对管传感器、蜂鸣器、电磁锁等元器件，当有人暴力开锁触发红外报警信息时，便会通过蜂鸣器报警。应用层PC端使用摄像头实现人脸识别，实现用户登录以及收银台解锁，通过TCP协议与云主机…☆16Jul 4, 2021Updated 4 years ago
- netease cloud music api for python☆15Jul 25, 2023Updated 2 years ago
- This repository implements various algorithms to solve LASSO problem via Matlab.☆11Jan 28, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 6 months ago
- ☆15Oct 15, 2020Updated 5 years ago
- RISC-V processor model☆11Nov 10, 2020Updated 5 years ago
- 计算机基础学习指南☆18Sep 30, 2020Updated 5 years ago
- Source code of the DCASE 2020 SELD submission "Audio Event Detection and Localization with Multitask Regression Network"☆17Jul 8, 2020Updated 5 years ago
- ☆14Jun 18, 2020Updated 5 years ago
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Apr 16, 2026Updated last month
- Linux 4 for Caninos Labrador V3☆14Sep 25, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- A Track-Wise Ensemble Event Independent Network for 3D Polyphonic Sound Event Localization and Detection☆23Nov 14, 2024Updated last year
- ☆20Mar 25, 2024Updated 2 years ago
- Build scripts of ci.rvperf.org☆12Apr 10, 2026Updated last month
- LoongArch常见的文档资料以及说明文档☆13Mar 6, 2024Updated 2 years ago
- DCASE2020 Challenge Task 2 baseline variants☆21Apr 2, 2020Updated 6 years ago
- This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…☆81Apr 15, 2025Updated last year