An FPGA-based RISC-V CPU
☆16Dec 7, 2021Updated 4 years ago
Alternatives and similar repositories for riscv
Users that are interested in riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 4 years ago
- 5 stage pipeline, single cycle risc-V implementation☆35Mar 9, 2024Updated 2 years ago
- A 5 stage-pipeline RV32I implementation in VHDL☆24Mar 13, 2020Updated 6 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 6 years ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆20Jun 3, 2023Updated 3 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆17Jan 4, 2020Updated 6 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- The seL4 microkernel with loongarch support, see official repositories at https://github.com/seL4☆21Jan 30, 2023Updated 3 years ago
- Audio/Speech/Acoustic based Digital Signal Processing☆10Oct 7, 2016Updated 10 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 5 years ago
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Jul 9, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 32-bit soft RISCV processor for FPGA applications☆20Nov 25, 2023Updated 2 years ago
- Design a cache by using Verilog☆13Jan 12, 2017Updated 9 years ago
- This repository contains getting started projects related to all PSoC4 pioneer kits.☆15Jul 9, 2026Updated 3 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆109Nov 14, 2018Updated 7 years ago
- RISC-V instruction set extensions for SM4 block cipher☆22Mar 6, 2020Updated 6 years ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 11 months ago
- netease cloud music api for python☆15Jul 25, 2023Updated 3 years ago
- Run rocket-chip on FPGA☆78Nov 16, 2025Updated 11 months ago
- Basic RISC-V Test SoC☆212Apr 7, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V processor model☆11Nov 10, 2020Updated 5 years ago
- 基于物联网技术以及人脸识别技术,系统底层采用ESP32开发板为核心,在ESP32开发板上接入了红 外对管传感器、蜂鸣器、电磁锁等元器件,当有人暴力开锁触发红外报警信息时,便会通过蜂鸣器报警。应用层PC端使用摄像头实现人脸识别,实现用户登录以及收银台解锁,通过TCP协议与云主机…☆16Jul 4, 2021Updated 5 years ago
- Mini RISC-V SOC☆13Nov 13, 2015Updated 10 years ago
- CLIProxyAPI反代Grok实现token自由,并且无限制内容☆14May 22, 2026Updated 5 months ago
- Processor CI project Website☆10Oct 5, 2026Updated 3 weeks ago
- Build scripts of ci.rvperf.org☆12Sep 23, 2026Updated last month
- ☆20Jul 21, 2020Updated 6 years ago
- 计算机基础学习指南☆18Sep 30, 2020Updated 6 years ago
- LoongArch常见的文档资料以及说明文档☆14Mar 6, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆16Feb 27, 2024Updated 2 years ago
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 3 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆48Mar 2, 2022Updated 4 years ago
- A small and simple rv32i core written in Verilog☆19Jul 29, 2022Updated 4 years ago
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Oct 2, 2026Updated 3 weeks ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆34Aug 31, 2023Updated 3 years ago