A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
☆35Mar 21, 2020Updated 6 years ago
Alternatives and similar repositories for fpga_test_soc
Users that are interested in fpga_test_soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 7 years ago
- Cortex-M0 DesignStart Wrapper☆24Aug 11, 2019Updated 7 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 3 years ago
- ☆13Nov 5, 2017Updated 8 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 10 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆23Jan 31, 2020Updated 6 years ago
- Neural Engine, 16 input channels☆19Oct 31, 2022Updated 3 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 3 years ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- Little handy Numerically controlled oscillator (NCO) Verilog RTL☆15Feb 15, 2024Updated 2 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Standalone Peripheral(SVD) Viewer extension extracted from cortex-debug, now works with any debugger☆17Updated this week
- Opensource embedded controller firmware for sipeed boards.☆45Feb 23, 2019Updated 7 years ago
- USB serial device (CDC-ACM)☆48Jun 28, 2020Updated 6 years ago
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆15Apr 11, 2023Updated 3 years ago
- Animals classification using CNN☆10Aug 29, 2019Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- Python interface to PCIE☆41Apr 30, 2018Updated 8 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated 2 years ago
- Basic RISC-V Test SoC☆209Apr 7, 2019Updated 7 years ago
- Kernel module that makes it possible to create virtual wifi devices each with a virtualized stack.☆11Dec 13, 2011Updated 14 years ago
- A flexible SoC emulator for ARM Cortex-M3☆15Apr 13, 2022Updated 4 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆42Oct 3, 2025Updated 10 months ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- UVM Testbench for synchronus fifo☆21Aug 28, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- bfloat16 dtype for numpy☆20Sep 25, 2023Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆53Dec 14, 2025Updated 8 months ago
- ☆18Apr 5, 2015Updated 11 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆16Nov 4, 2020Updated 5 years ago
- An open source FPGA design for DSLogic☆175Jul 8, 2014Updated 12 years ago
- RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo☆13Mar 7, 2020Updated 6 years ago
- Cortex_m0软核源码，可以在FPGA上直接跑，包含UART、定时器这些外设，可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆27Mar 15, 2021Updated 5 years ago