A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
☆36Mar 21, 2020Updated 6 years ago
Alternatives and similar repositories for fpga_test_soc
Users that are interested in fpga_test_soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 8 years ago
- Cortex-M0 DesignStart Wrapper☆24Aug 11, 2019Updated 7 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆23Jan 31, 2020Updated 6 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 3 years ago
- APB Timer Unit☆14Oct 30, 2025Updated last year
- A simple UVM project. The DUT(RTL) is a simple amplifier.☆10Sep 28, 2022Updated 4 years ago
- Neural Engine, 16 input channels☆20Oct 31, 2022Updated 4 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated 2 years ago
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆42Oct 13, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 进制转换, ADC分压, ADC按键, 数码管取模, DCDC计算器等基础功能☆12Jun 22, 2025Updated last year
- Little handy Numerically controlled oscillator (NCO) Verilog RTL☆15Feb 15, 2024Updated 2 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- RISC-V compliant Timer IP☆14May 10, 2024Updated 2 years ago
- bl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706 and other series of RISC-V b…☆10Sep 7, 2026Updated last month
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 7 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated 2 years ago
- Basic RISC-V Test SoC☆212Apr 7, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated 2 years ago
- USB serial device (CDC-ACM)☆49Jun 28, 2020Updated 6 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Animals classification using CNN☆10Aug 29, 2019Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆16Apr 11, 2023Updated 3 years ago
- servo motor control with FPGA☆10Nov 14, 2015Updated 10 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆87Aug 9, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A flexible SoC emulator for ARM Cortex-M3☆15Apr 13, 2022Updated 4 years ago
- Opensource embedded controller firmware for sipeed boards.☆45Feb 23, 2019Updated 7 years ago
- Updated version of the XUP Workshops☆19Aug 10, 2018Updated 8 years ago
- Standalone Peripheral(SVD) Viewer extension extracted from cortex-debug, now works with any debugger☆21Oct 15, 2026Updated 2 weeks ago
- bfloat16 dtype for numpy☆20Sep 25, 2023Updated 3 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件，并在 ARM＋FPGA 完成项目部署，实现通过摄取图片并通过 ARM＋FPGA 综合部署和加速识别算法，并通过显示驱动，在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 4 years ago