ultraembedded / fpga_test_soc
A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
☆29Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for fpga_test_soc
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆20Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆37Updated 3 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆57Updated 2 years ago
- USB 2.0 Device IP Core☆52Updated 7 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 4 years ago
- UART -> AXI Bridge☆55Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆75Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- ☆16Updated 5 years ago
- ☆33Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- configurable cordic core in verilog☆46Updated 10 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆18Updated 9 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆35Updated 4 months ago
- I2C controller core☆33Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆21Updated 6 years ago
- QSPI for SoC☆16Updated 5 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆53Updated 2 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- turbo 8051☆28Updated 7 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆31Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago