CMU-SAFARI / MemSchedSim
This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based out-of-order core frontend and models memory scheduling policies such as FRFCFS, ATLAS, TCM, BLISS. Based on the ICCD 2014 paper by Subramanian et al. at http://users.ece.cmu.edu/~omutlu/pub/bliss-memory-schedule…
☆10Updated 9 years ago
Alternatives and similar repositories for MemSchedSim:
Users that are interested in MemSchedSim are comparing it to the libraries listed below
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 5 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend a…☆13Updated 8 years ago
- ☆18Updated 4 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 6 years ago
- A parallel and distributed simulator for thousand-core chips☆22Updated 6 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Memory consistency model checking and test generation library.☆14Updated 8 years ago
- Artifact, reproducibility, and testing utilites for gem5☆21Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆10Updated 6 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆18Updated 4 years ago
- The OpenPiton Platform☆28Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆21Updated 2 weeks ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 2 years ago
- ☆15Updated last year
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆18Updated 9 years ago
- ☆12Updated 9 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Updated 9 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year