Alternatives and similar repositories for vdt-plugin:

Users that are interested in vdt-plugin are comparing it to the libraries listed below

• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• UGent-HES / tlut_flow
  TLUT tool flow for parameterised configurations for FPGAs
  ☆16Updated 7 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆45Updated 4 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• knielsen / ice40_viewer
  ☆59Updated last year
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 8 months ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆38Updated 7 years ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• Elphel / x393
  mirror of https://git.elphel.com/Elphel/x393
  ☆39Updated 2 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• ZipCPU / wbhyperram
  A cross platform, formally verified, open source, hyperRAM controller with simulator
  ☆11Updated 6 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆43Updated 9 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆36Updated 4 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆32Updated 4 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 5 years ago
• wware / myblaze
  MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…
  ☆17Updated 11 years ago
• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆20Updated 9 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago