www-asics-ws / usb1_deviceLinks
USB 1.1 Device IP Core
☆21Updated 7 years ago
Alternatives and similar repositories for usb1_device
Users that are interested in usb1_device are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- ☆22Updated 3 weeks ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated this week
- Wishbone <-> AXI converters☆14Updated 10 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- Generic Logic Interfacing Project☆46Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- ☆33Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- PicoRV☆44Updated 5 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- Simplified environment for litex☆14Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 4 years ago
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- RISC-V processor☆31Updated 3 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- PulseRain FP51-1T MCU core☆9Updated 7 years ago