YosysHQ / VlogHammerLinks
A Verilog Synthesis Regression Test
☆37Updated last year
Alternatives and similar repositories for VlogHammer
Users that are interested in VlogHammer are comparing it to the libraries listed below
Sorting:
- Benchmarks for Yosys development☆24Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Mutation Cover with Yosys (MCY)☆85Updated 3 weeks ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Xilinx Unisim Library in Verilog☆81Updated 5 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 8 months ago
- ☆23Updated 2 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆27Updated 5 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Demo SoC for SiliconCompiler.☆60Updated 2 months ago
- PicoRV☆44Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆34Updated 3 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 4 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 4 months ago
- Yet Another VHDL tool☆31Updated 8 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago