YosysHQ / VlogHammerLinks
A Verilog Synthesis Regression Test
☆37Updated last year
Alternatives and similar repositories for VlogHammer
Users that are interested in VlogHammer are comparing it to the libraries listed below
Sorting:
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Mutation Cover with Yosys (MCY)☆86Updated last week
- Collection of test cases for Yosys☆18Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago
- OpenFPGA☆34Updated 7 years ago
- ☆23Updated 4 months ago
- mantle library☆44Updated 2 years ago
- A time-predictable processor for mixed-criticality systems☆59Updated 10 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated this week
- IRSIM switch-level simulator for digital circuits☆34Updated 5 months ago
- Yosys Plugins☆21Updated 6 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Demo SoC for SiliconCompiler.☆60Updated last week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆56Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago