YosysHQ / VlogHammerLinks
A Verilog Synthesis Regression Test
☆37Updated last year
Alternatives and similar repositories for VlogHammer
Users that are interested in VlogHammer are comparing it to the libraries listed below
Sorting:
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆87Updated 3 weeks ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- A time-predictable processor for mixed-criticality systems☆58Updated 10 months ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 2 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated 2 weeks ago
- ☆23Updated 4 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- IRSIM switch-level simulator for digital circuits☆34Updated 5 months ago
- PicoRV☆44Updated 5 years ago
- Yosys Plugins☆22Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- SoftCPU/SoC engine-V☆54Updated 6 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- OpenFPGA☆34Updated 7 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Visual Simulation of Register Transfer Logic☆101Updated last month
- Experiments with Yosys cxxrtl backend☆50Updated 8 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago