Alternatives and similar repositories for spacex_uart

Users that are interested in spacex_uart are comparing it to the libraries listed below

• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆43Updated 9 months ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆65Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated last year
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated 10 months ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆82Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆91Updated 3 years ago
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 4 years ago
• open-design / riscv-soc-cores
  ☆40Updated 4 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• freecores / uart16550
  UART 16550 core
  ☆37Updated 11 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• wavedrom / vcd-samples
  sample VCD files
  ☆39Updated 2 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆96Updated 5 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 2 months ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 5 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆44Updated 4 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆33Updated 8 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆47Updated 5 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆57Updated this week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆51Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• shalan / MS_QSPI_XIP_CACHE
  AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
  ☆13Updated 2 years ago
• FHDO-ICLAB / MIPI-CSI-2-HDMI-Bridge
  This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…
  ☆18Updated 3 months ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆66Updated last week