asicguy / spacex_uart
Project and presentation for SpaceX Application
☆14Updated 7 years ago
Alternatives and similar repositories for spacex_uart:
Users that are interested in spacex_uart are comparing it to the libraries listed below
- Wishbone interconnect utilities☆39Updated 2 months ago
- Verilog Repository for GIT☆32Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Contains source code for sin/cos table verification using UVM☆20Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- UART models for cocotb☆28Updated 2 years ago
- UART 16550 core☆34Updated 10 years ago
- PCI bridge☆18Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- USB 1.1 Host and Function IP core☆21Updated 10 years ago
- Minimal DVI / HDMI Framebuffer☆80Updated 4 years ago
- ☆37Updated 4 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated last year
- WISHBONE Interconnect☆11Updated 7 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 3 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆26Updated 2 years ago
- Verilog wishbone components☆114Updated last year
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆28Updated 6 years ago