maltanar / spmv-vector-cache
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
☆10Updated 9 years ago
Alternatives and similar repositories for spmv-vector-cache:
Users that are interested in spmv-vector-cache are comparing it to the libraries listed below
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- ☆24Updated 4 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- ☆35Updated 4 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 8 months ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆12Updated 8 months ago
- ☆29Updated 6 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆12Updated 3 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆16Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated last week
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- ☆26Updated 7 years ago
- NeuraChip Accelerator Simulator☆11Updated last year
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆19Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago