maltanar / spmv-vector-cacheLinks
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
☆10Updated 10 years ago
Alternatives and similar repositories for spmv-vector-cache
Users that are interested in spmv-vector-cache are comparing it to the libraries listed below
Sorting:
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Updated 7 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- ☆24Updated 5 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- CNN accelerator☆29Updated 8 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- ☆36Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Updated 7 months ago
- Domain-Specific Architecture Generator 2☆22Updated 3 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- ☆29Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Papers, Posters, Presentations, Documentation...☆19Updated 2 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆18Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆42Updated 10 months ago
- cycle accurate Network-on-Chip Simulator☆32Updated last month
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago