maltanar / spmv-vector-cacheLinks
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
☆10Updated 10 years ago
Alternatives and similar repositories for spmv-vector-cache
Users that are interested in spmv-vector-cache are comparing it to the libraries listed below
Sorting:
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆20Updated 7 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- ☆36Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 2 months ago
- ☆24Updated 5 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 7 years ago
- ☆29Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- ☆40Updated 8 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 10 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- corundum work on vu13p☆22Updated 2 years ago
- A parallel and distributed simulator for thousand-core chips☆27Updated 7 years ago