maltanar / spmv-vector-cacheLinks
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
☆10Updated 9 years ago
Alternatives and similar repositories for spmv-vector-cache
Users that are interested in spmv-vector-cache are comparing it to the libraries listed below
Sorting:
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last week
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆16Updated 5 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆36Updated 4 years ago
- ☆29Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- ☆15Updated 9 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆13Updated 9 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆24Updated 4 years ago
- ☆15Updated 3 years ago