maltanar / spmv-vector-cache
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
☆10Updated 9 years ago
Alternatives and similar repositories for spmv-vector-cache
Users that are interested in spmv-vector-cache are comparing it to the libraries listed below
Sorting:
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- ☆35Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- Documentation for the entire CGRAFlow☆19Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 8 months ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆25Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- CNN accelerator☆27Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- ☆12Updated 9 months ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆24Updated 4 years ago
- ☆21Updated 2 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated last month
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆35Updated 4 months ago