ucb-bar / ccbenchLinks
Memory System Microbenchmarks
☆63Updated 2 years ago
Alternatives and similar repositories for ccbench
Users that are interested in ccbench are comparing it to the libraries listed below
Sorting:
- Utilities to measure read access times of caches, memory, and hardware prefetches for simple and fused operations☆84Updated last year
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- ESESC: A Fast Multicore Simulator☆138Updated 3 years ago
- ☆20Updated 5 years ago
- Python Cache Hierarchy Simulator☆99Updated last month
- SST Architectural Simulation Components and Libraries☆101Updated this week
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- ☆33Updated 5 years ago
- A wrapper for the SPEC CPU2006 benchmark suite.☆89Updated 4 years ago
- Collection of synchronization micro-benchmarks and traces from infrastructure applications☆46Updated last month
- HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs☆30Updated 11 months ago
- DRAM Bank-Aware Kernel Memory Allocator☆42Updated 8 months ago
- A fast and scalable x86-64 multicore simulator☆31Updated 4 years ago
- ☆17Updated 3 years ago
- Source code for the Base-Delta-Immediate Compression Algorithm (described in the PACT 2012 paper by Pekhimenko et al. at http://users.ece…☆26Updated 10 years ago
- ☆67Updated 7 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆12Updated 5 years ago
- ☆138Updated last month
- Multi2Sim source code☆132Updated 6 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- A parallel and distributed simulator for thousand-core chips☆25Updated 7 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆49Updated last week
- Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors☆41Updated 6 years ago
- ☆168Updated 4 years ago
- PARSEC Benchmark http://parsec.cs.princeton.edu 3.0-beta-20150206 ported to Ubuntu 22.04 and with proper version control and SPLASH2 port…☆98Updated 9 months ago
- A heterogeneous architecture timing model simulator.☆165Updated last week
- A parallel, distributed simulator for multicores.☆184Updated 9 years ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆116Updated 3 months ago
- The Splash-3 benchmark suite☆44Updated 2 years ago