Alternatives and similar repositories for ccbench

Users that are interested in ccbench are comparing it to the libraries listed below

• afborchert / pointer-chasing
  Utilities to measure read access times of caches, memory, and hardware prefetches for simple and fused operations
  ☆84Updated last year
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago
• aakahlow / gem5Valid_Haswell
  ☆20Updated 5 years ago
• masc-ucsc / esesc
  ESESC: A Fast Multicore Simulator
  ☆138Updated 3 years ago
• mattsinc / heterosync
  HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs
  ☆30Updated 11 months ago
• CMU-SAFARI / MemBen
  Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …
  ☆22Updated 4 years ago
• ARM-software / synchronization-benchmarks
  Collection of synchronization micro-benchmarks and traces from infrastructure applications
  ☆46Updated 3 weeks ago
• umd-memsys / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆12Updated 5 years ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆88Updated 4 years ago
• pcie-bench / pcie-model
  ☆66Updated 6 months ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆33Updated 5 years ago
• hanhwi / SimPoint
  ☆15Updated 3 years ago
• parsa-epfl / qflex
  Quick & Flexible Rack-Scale Computer Architecture Simulator
  ☆46Updated this week
• SakalisC / Splash-3
  The Splash-3 benchmark suite
  ☆44Updated 2 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆41Updated 2 years ago
• sstsimulator / sst-elements
  SST Architectural Simulation Components and Libraries
  ☆97Updated last week
• heechul / palloc
  DRAM Bank-Aware Kernel Memory Allocator
  ☆42Updated 7 months ago
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• gthparch / macsim
  A heterogeneous architecture timing model simulator.
  ☆165Updated 8 months ago
• LvNA-system / labeled-RISC-V
  ☆168Updated 4 years ago
• aliireza / slice-aware
  Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors
  ☆41Updated 6 years ago
• cirosantilli / parsec-benchmark
  PARSEC Benchmark http://parsec.cs.princeton.edu 3.0-beta-20150206 ported to Ubuntu 22.04 and with proper version control and SPLASH2 port…
  ☆97Updated 9 months ago
• WukLab / Clio
  Clio, ASPLOS'22.
  ☆78Updated 3 years ago
• RRZE-HPC / pycachesim
  Python Cache Hierarchy Simulator
  ☆99Updated 3 weeks ago
• stanford-mast / zsim
  A fast and scalable x86-64 multicore simulator
  ☆31Updated 4 years ago
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆25Updated 7 years ago
• mit-carbon / Graphite
  A parallel, distributed simulator for multicores.
  ☆184Updated 9 years ago
• jfunston / MultiCacheSim
  A cache simulator designed to be used with memory access traces obtained from Pin (www.pintool.org)
  ☆23Updated 7 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆23Updated 4 years ago
• Multi2Sim / multi2sim
  Multi2Sim source code
  ☆130Updated 6 years ago