Alternatives and similar repositories for ptxas-wrapper

Users that are interested in ptxas-wrapper are comparing it to the libraries listed below

• vortexgpgpu / NVPTX-SPIRV-Translator
  The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.
  ☆39Updated 3 years ago
• pnnl / COMET
  ☆41Updated 2 weeks ago
• spcl / SMI
  Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware
  ☆16Updated 3 years ago
• ProjectPhysX / PTXprofiler
  A simple profiler to count Nvidia PTX assembly instructions of OpenCL/SYCL/CUDA kernels for roofline model analysis.
  ☆52Updated 2 months ago
• KhronosGroup / SYCL_Reference
  SYCL Reference Manual
  ☆28Updated last year
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆19Updated last year
• mattsinc / heterosync
  HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs
  ☆30Updated 8 months ago
• decodecudabinary / Decoding-CUDA-Binary
  ☆52Updated 5 years ago
• hkust-adsl / gass
  ☆35Updated 3 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 9 months ago
• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 8 months ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆31Updated 2 years ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated 3 months ago
• gthparch / NVPTX-SPIRV-Translator
  ☆21Updated 3 years ago
• makslevental / mlir-wheels
  ☆23Updated 3 weeks ago
• sderek / CUDAAdvisor
  CUDAAdvisor: a GPU profiling tool
  ☆49Updated 6 years ago
• NVlabs / ptxmemorymodel
  ☆55Updated 6 years ago
• ychen306 / vegen
  ☆29Updated 2 years ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆14Updated 2 years ago
• CUDACommunity / CUDACommunityMeetup2021
  ☆23Updated 3 years ago
• gvsoc / gvsoc
  ☆19Updated last week
• RRZE-HPC / asmbench
  A Benchmark Toolkit for Assembly Instructions Using the LLVM JIT
  ☆16Updated 4 years ago
• illinois-impact / klap
  A source-to-source compiler for optimizing CUDA dynamic parallelism by aggregating launches
  ☆15Updated 5 years ago
• Jokeren / GPA
  GPU Performance Advisor
  ☆65Updated 2 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆23Updated 6 months ago
• michalpaszkowski / LLVM-Canon
  LLVM-Canon aims to transform LLVM modules into a canonical form by reordering and renaming instructions while preserving the same semanti…
  ☆15Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last week
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆22Updated last year
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago