tsinghua-ideal / spada-simLinks
The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
☆37Updated 2 years ago
Alternatives and similar repositories for spada-sim
Users that are interested in spada-sim are comparing it to the libraries listed below
Sorting:
- ☆33Updated 3 weeks ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆28Updated 6 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆22Updated 4 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆56Updated 6 months ago
- ☆26Updated 3 years ago
- NeuraChip Accelerator Simulator☆12Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆13Updated 2 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆81Updated last month
- ☆31Updated last year
- ☆25Updated last year
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆34Updated 6 months ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆68Updated 3 months ago
- A list of our chiplet simulaters☆33Updated 2 months ago
- ☆73Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆19Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆81Updated last year
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- Processing in Memory Emulation☆20Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆72Updated 6 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆38Updated last year
- ☆24Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- ☆28Updated 2 years ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆71Updated last month