fpgasystems / fpga-hyperloglog
FPGA-based HyperLogLog Accelerator
☆12Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for fpga-hyperloglog
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- A multicore microprocessor test harness for measuring interference☆13Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆28Updated 3 weeks ago
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- Memory consistency modelling using Alloy☆28Updated 3 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 6 months ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆29Updated last month
- Chisel library for Unum Type-III Posit Arithmetic☆32Updated 7 months ago
- ☆11Updated 2 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆19Updated 4 years ago
- Xilinx Modifications to Halide☆10Updated 3 years ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated 2 months ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- Wrapper for ETH Ariane Core☆19Updated 3 months ago
- ☆23Updated 3 years ago
- Floating point modules for CHISEL☆28Updated 10 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- ☆10Updated 2 years ago
- SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…☆15Updated 4 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated last week
- GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and comp…☆12Updated 2 years ago
- A Hardware Pipeline Description Language☆41Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- firrtlator is a FIRRTL C++ library☆21Updated 7 years ago
- compiling DSLs to high-level hardware instructions☆21Updated 2 years ago
- ☆41Updated 3 years ago
- This repo includes XiangShan's function units☆15Updated 2 weeks ago
- Caribou: Distributed Smart Storage built with FPGAs☆64Updated 6 years ago
- Verilog AST☆19Updated 11 months ago