Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA
☆23May 20, 2019Updated 6 years ago
Alternatives and similar repositories for AXI_DMA_FIFO
Users that are interested in AXI_DMA_FIFO are comparing it to the libraries listed below
Sorting:
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- ☆18Jan 30, 2018Updated 8 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 5 years ago
- Gigabit Ethernet UDP communication driver☆81Jul 26, 2019Updated 6 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- ☆15Jan 9, 2022Updated 4 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆28Mar 3, 2024Updated 2 years ago
- PYNQ-Z1 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx☆12Jun 16, 2021Updated 4 years ago
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- SDK library for low-end CH32 RISC-V microcontrollers☆21Jan 27, 2026Updated last month
- CNN-to-FPGA-framework for small CNN, written in VHDL and Python☆23Jun 8, 2021Updated 4 years ago
- A small program written in C showing implementations of common image dithering algorithms.☆12Sep 23, 2016Updated 9 years ago
- This is for uvm_tb_gen☆52Feb 13, 2025Updated last year
- 💾 FreeRTOS port for the NEORV32 RISC-V Processor.☆13Updated this week
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- Polar Codes Implementation on Vhdl☆14Jun 4, 2016Updated 9 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆19Jul 22, 2021Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Nov 19, 2023Updated 2 years ago
- Capture data from multiple ADCs concurrently using an FPGA. Stream the captured data out over ethernet + UDP. Tested on the Spartan 6 XC6…☆17Dec 10, 2016Updated 9 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- Sparse MerkleTree implementation in Rust☆19Oct 16, 2019Updated 6 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆58Jun 23, 2021Updated 4 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆45Jun 7, 2017Updated 8 years ago
- Decode Audio files using Arduino☆14Aug 1, 2020Updated 5 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 6 years ago
- ☆13Jan 28, 2026Updated last month
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- AIChip 2021 project, NCKU☆17May 6, 2021Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago