Alternatives and similar repositories for FPGA_CDR_core

Users that are interested in FPGA_CDR_core are comparing it to the libraries listed below

• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆71Updated 8 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆141Updated 2 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆214Updated last year
• maswx / vu13p
  国产VU13P加速卡资料
  ☆79Updated 7 months ago
• jamieiles / uart
  Verilog UART
  ☆183Updated 12 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆77Updated last year
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆130Updated 5 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆75Updated last year
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆60Updated 9 years ago
• WangXuan95 / FPGA-MPEG2-encoder
  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
  ☆138Updated last year
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆62Updated 3 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆75Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆158Updated 2 years ago
• VideoGPU / MIPI_CSI2_TX
  VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
  ☆76Updated 2 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆45Updated 4 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆141Updated last year
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆68Updated 4 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆142Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆40Updated last month
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆124Updated 3 years ago
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆79Updated last month
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆58Updated 3 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Updated 2 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆236Updated 2 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆49Updated 2 years ago