FPGA implementation of a CDR targeting a Xilinx Kintex-7 for data rates up to 250 MHz
☆19Nov 15, 2021Updated 4 years ago
Alternatives and similar repositories for FPGA_CDR_core
Users that are interested in FPGA_CDR_core are comparing it to the libraries listed below
Sorting:
- 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC-balance and bounded disparity, which is used for telecommunic…☆12Jun 8, 2021Updated 4 years ago
- Build an CCD camera for astrophotography☆15Oct 16, 2023Updated 2 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Jul 12, 2020Updated 5 years ago
- ☆14Feb 3, 2016Updated 10 years ago
- A software-based small signal analysis tool for digital controlled power supplies and more☆18May 2, 2023Updated 2 years ago
- Support for zScale on Spartan6 FPGAs☆15Aug 3, 2015Updated 10 years ago
- A Docker image for Mentor/Siemens Questa☆13Sep 26, 2023Updated 2 years ago
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- Simple power switch using a push button. Push to turn on, hold to turn off.☆16Oct 11, 2024Updated last year
- Flexible VHDL library☆194Jun 28, 2023Updated 2 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- A summary of CASSI reconstruction algorithms, including performance, complexity, paper links and codes.☆18Nov 25, 2022Updated 3 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 2 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- KASIRGA - GUN | RV32IMCX☆11Aug 14, 2024Updated last year
- Fullsearch based Motion Estimation Processor written in Verilog-HDL☆11Feb 19, 2017Updated 9 years ago
- HDL components to build a customized Wishbone crossbar switch☆14May 30, 2019Updated 6 years ago
- Synchronous Slave FIFO Interface between Xilinx Spartan 3E and Cypress FX3☆15Mar 11, 2015Updated 11 years ago
- RFNoC out-of-tree module for a channelizer☆16Mar 14, 2018Updated 8 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 4 years ago
- Suite of tools for noise analysis in Python☆17Sep 8, 2024Updated last year
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Crossplatform port of original Quake Remake mod with modern Xash3D FWGS build☆13Feb 10, 2025Updated last year
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- A set of small Verilog projects, to simulate and implement on FPGA development boards☆15Mar 5, 2018Updated 8 years ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆17Jan 21, 2026Updated 2 months ago
- A ceiling mounted camera which looks around between defined points. Can detect and track a player character.☆14Mar 17, 2023Updated 3 years ago
- Homemade power meter using NRF42832 and ANT+☆25Jul 9, 2021Updated 4 years ago
- Example applications for UHD/RFNoC☆19Mar 8, 2022Updated 4 years ago
- Implementation of DeepID2☆18Sep 5, 2016Updated 9 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆39Sep 18, 2024Updated last year
- SocKit 1-wire (onewire) master☆19Aug 5, 2012Updated 13 years ago
- AXI Stream UART (verilog)☆12Oct 3, 2019Updated 6 years ago
- ☆15Jan 8, 2024Updated 2 years ago
- ☆16Aug 9, 2023Updated 2 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year