FilMarini / FPGA_CDR_core

Related projects ⓘ

Alternatives and complementary repositories for FPGA_CDR_core

• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆52Updated 7 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆29Updated 9 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆67Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆58Updated 3 years ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆57Updated 9 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 4 years ago
• VideoGPU / MIPI_CSI2_TX
  VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
  ☆60Updated last year
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆87Updated 4 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆39Updated 3 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆51Updated 3 years ago
• jiacaiyuan / i2c_slave
  I2C slave Verilog Design and TestBench
  ☆16Updated 5 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆16Updated 5 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆114Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆47Updated 5 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆45Updated 2 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆55Updated 9 months ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆185Updated 6 months ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆39Updated last year
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆40Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago
• antmicro / nvme-verilog-pcie
  ☆47Updated 2 years ago
• Tommydag / CAN-Bus-Controller
  An CAN bus Controller implemented in Verilog
  ☆41Updated 9 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆34Updated 9 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆47Updated 10 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆28Updated 8 years ago
• pendkeomkar / SPI
  Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…
  ☆17Updated 6 years ago