FPGA implementation of a CDR targeting a Xilinx Kintex-7 for data rates up to 250 MHz
☆19Nov 15, 2021Updated 4 years ago
Alternatives and similar repositories for FPGA_CDR_core
Users that are interested in FPGA_CDR_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC-balance and bounded disparity, which is used for telecommunic…☆12Jun 8, 2021Updated 5 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 9 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Jul 12, 2020Updated 5 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆14Feb 3, 2016Updated 10 years ago
- Support for zScale on Spartan6 FPGAs☆15Aug 3, 2015Updated 10 years ago
- A Docker image for Mentor/Siemens Questa☆13Sep 26, 2023Updated 2 years ago
- PyTorch codes for reproducing TIP 2019 paper "HyperReconNet: Joint Coded Aperture Optimization and Image Reconstruction for Compressive H…☆10Apr 13, 2022Updated 4 years ago
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- Simple power switch using a push button. Push to turn on, hold to turn off.☆16Oct 11, 2024Updated last year
- Flexible VHDL library☆196Jun 28, 2023Updated 2 years ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A summary of CASSI reconstruction algorithms, including performance, complexity, paper links and codes.☆18Nov 25, 2022Updated 3 years ago
- Fullsearch based Motion Estimation Processor written in Verilog-HDL☆11Feb 19, 2017Updated 9 years ago
- Collect some IC specs for learning.☆23Jun 25, 2024Updated last year
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- Synchronous Slave FIFO Interface between Xilinx Spartan 3E and Cypress FX3☆15Mar 11, 2015Updated 11 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 4 years ago
- Acceleration for an s-curve shaped speed☆12Jun 19, 2024Updated last year
- Suite of tools for noise analysis in Python☆17Sep 8, 2024Updated last year
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs☆19Sep 2, 2019Updated 6 years ago
- RFNoC out-of-tree module for a channelizer☆17Mar 14, 2018Updated 8 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 8 years ago
- A set of small Verilog projects, to simulate and implement on FPGA development boards☆15Mar 5, 2018Updated 8 years ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆18Jan 21, 2026Updated 4 months ago
- A ceiling mounted camera which looks around between defined points. Can detect and track a player character.☆14Mar 17, 2023Updated 3 years ago
- Implementation of DeepID2☆18Sep 5, 2016Updated 9 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆17Jan 10, 2018Updated 8 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆39Sep 18, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SocKit 1-wire (onewire) master☆19Aug 5, 2012Updated 13 years ago
- A JavaScript graph library☆10May 20, 2014Updated 12 years ago
- DroidOscillo firmware☆10May 8, 2017Updated 9 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year
- ☆14Oct 6, 2023Updated 2 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Apr 8, 2026Updated 2 months ago
- DOA 估计和自适应波束形成☆14Jun 17, 2019Updated 6 years ago