Logicademy / HDLGen-ChatGPTLinks
HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
☆36Updated last year
Alternatives and similar repositories for HDLGen-ChatGPT
Users that are interested in HDLGen-ChatGPT are comparing it to the libraries listed below
Sorting:
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Updated 10 months ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆28Updated 6 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33Updated last year
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated last week
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆70Updated this week
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- SDRAM controller for MIPSfpga+ system☆24Updated 5 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- ☆26Updated 2 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Updated 10 months ago
- A flexible and scalable development platform for modern FPGA projects.☆39Updated last week
- Open Source PHY v2☆33Updated last year
- Extensible FPGA control platform☆61Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆40Updated 11 months ago
- SAR ADC on tiny tapeout☆45Updated last year
- Framework Open EDA Gui☆73Updated last year
- high level VHDL floating point library for synthesis in fpga☆18Updated last month
- An open-source HDL register code generator fast enough to run in real time.☆82Updated last week
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 3 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- ☆60Updated 4 years ago