BCH error-correcting code MATLAB simulator - University of Michigan (Winter, 2011)
☆13Nov 14, 2019Updated 6 years ago
Alternatives and similar repositories for bch
Users that are interested in bch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BCH (Bose-Chaudhuri-Hocquenghem) encoder and decoder built from scratch in matlab as course project for EE5160: Error Control Coding☆18Mar 31, 2017Updated 9 years ago
- A Performance Analysis and Simulation of BCH Code in Matlab☆13Feb 26, 2022Updated 4 years ago
- Polar coding, decoding, and testing☆13Oct 11, 2023Updated 2 years ago
- User BCH encode/decode library based on bch module from linux kernel☆33May 22, 2015Updated 11 years ago
- Simple python implementation of binary BCH error-correcting code☆33Jan 12, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- C library for ECC-SM2 public encrypt☆10Dec 17, 2016Updated 9 years ago
- Verilog based BCH encoder/decoder☆137Sep 26, 2022Updated 3 years ago
- Error Correction Codes - C☆11May 26, 2019Updated 7 years ago
- 电子科大学生排课脚本代码☆18Aug 20, 2022Updated 3 years ago
- Easy swapping of text in Vim☆20Apr 6, 2020Updated 6 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- KYSM4是一个基于SM4国密算法的Objective-C的国密SM4算法类库☆11Mar 7, 2019Updated 7 years ago
- Image Compression on COCO Dataset using Convolution AutoEncoders☆12Feb 24, 2019Updated 7 years ago
- my emacs config☆13Mar 12, 2026Updated 4 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Code for liver lesion segmentation using different architectures☆17Apr 26, 2020Updated 6 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- Some useful functions to process pdf file☆20Sep 13, 2025Updated 10 months ago
- Image compression using Variational Autoencoder and Generative Adversarial Networks.☆11Feb 25, 2019Updated 7 years ago
- Digital signal processing library☆18Oct 13, 2020Updated 5 years ago
- Implementing the MATLAB example using 5G toolbox and Deep Learning Tolbox☆15Sep 1, 2021Updated 4 years ago
- ☆12Oct 26, 2023Updated 2 years ago
- X86 Instruction Profiler☆13May 19, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- Code related to ’Beyond spectral gap: The role of the topology in decentralized learning‘.☆14Jun 7, 2022Updated 4 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 3 years ago
- Netfilter firewall to capture and intercept packets on port 80. Performs simple analysis and packet editing.☆12Jan 27, 2016Updated 10 years ago
- Autoencoder-based image compression using pictures of the surface of Mars.☆18Jun 12, 2020Updated 6 years ago
- This project is made to generate Polar decoders (unrolled decoders).☆15May 31, 2025Updated last year
- My graduation project.☆13Oct 12, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Download all songs or individual songs of Netease Cloud Music Songs (下载网易云音乐歌单所有歌曲或单独歌曲)☆16Dec 17, 2023Updated 2 years ago
- Synchronous Slave FIFO Interface between Xilinx Spartan 3E and Cypress FX3☆15Mar 11, 2015Updated 11 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆15Apr 11, 2023Updated 3 years ago
- ☆17Aug 4, 2014Updated 11 years ago