momalab / CoPHEELinks
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
☆36Updated last year
Alternatives and similar repositories for CoPHEE
Users that are interested in CoPHEE are comparing it to the libraries listed below
Sorting:
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆19Updated 3 years ago
- ☆27Updated 2 years ago
- ☆13Updated 10 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆43Updated this week
- ☆82Updated last year
- ☆14Updated 3 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Updated 10 years ago
- ☆28Updated 5 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- ☆17Updated 4 months ago
- CNN accelerator☆29Updated 8 years ago
- ☆25Updated 4 years ago
- corundum work on vu13p☆23Updated 2 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Defense/Attack PUF Library (DA PUF Library)☆55Updated 5 years ago
- Alveo Versal Example Design☆56Updated last week
- FIPS 202 compliant SHA-3 core in Verilog☆23Updated 5 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆13Updated 6 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- Spike with a coherence supported cache model☆14Updated last year
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆42Updated 6 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆40Updated last year
- ☆17Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 8 months ago