momalab / CoPHEELinks
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
☆33Updated last year
Alternatives and similar repositories for CoPHEE
Users that are interested in CoPHEE are comparing it to the libraries listed below
Sorting:
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆18Updated 3 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- ☆13Updated 10 years ago
- ☆80Updated last year
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- ☆26Updated 2 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- ☆27Updated 5 years ago
- ☆23Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 11 years ago
- ☆18Updated 2 months ago
- ☆67Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- ☆27Updated last month
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- CNN accelerator☆27Updated 8 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆49Updated 10 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆40Updated 5 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 7 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆22Updated 4 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- ☆29Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆76Updated 2 weeks ago