momalab / CoPHEELinks
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
☆35Updated last year
Alternatives and similar repositories for CoPHEE
Users that are interested in CoPHEE are comparing it to the libraries listed below
Sorting:
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆19Updated 3 years ago
- ☆13Updated 10 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- ☆81Updated last year
- corundum work on vu13p☆23Updated 2 years ago
- ☆26Updated 2 years ago
- ☆25Updated 4 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 10 years ago
- ☆27Updated 3 months ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆39Updated last week
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Alveo Versal Example Design☆48Updated this week
- CNN accelerator☆27Updated 8 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- ☆27Updated 6 years ago
- ☆14Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆36Updated 3 months ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆23Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- RISC-V instruction set extensions for SM4 block cipher☆20Updated 5 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a …☆25Updated 6 months ago
- Coarse Grained Reconfigurable Array☆20Updated 2 weeks ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆32Updated 3 years ago