momalab / CoPHEELinks
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
☆31Updated last year
Alternatives and similar repositories for CoPHEE
Users that are interested in CoPHEE are comparing it to the libraries listed below
Sorting:
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆19Updated 2 years ago
- ☆13Updated 10 years ago
- Verilog RTL Implementation of DNN☆10Updated 6 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- ☆25Updated last year
- ☆22Updated 3 years ago
- ☆14Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆34Updated 4 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago
- ☆27Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated last year
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Updated 6 years ago
- Alveo Versal Example Design☆41Updated 3 months ago
- The hardware implementation of Poseidon hash function in SpinalHDL☆19Updated 3 years ago
- ☆20Updated 5 years ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- ☆22Updated 9 months ago
- sram/rram/mram.. compiler☆35Updated last year
- corundum work on vu13p☆18Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆20Updated 9 years ago
- ☆28Updated 4 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆12Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 5 months ago