Alternatives and similar repositories for Digital-IDE:

Users that are interested in Digital-IDE are comparing it to the libraries listed below

• Digital-EDA / Digital-IDE
  All in one vscode plugin for HDL development
  ☆478Updated this week
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆191Updated 6 months ago
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆526Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆138Updated 2 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆743Updated 3 years ago
• xupsh / Digital-Design-Lab
  ☆213Updated 3 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆195Updated last year
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆403Updated 5 years ago
• ljgibbslf / SM3_core
  ☆139Updated 4 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆250Updated last year
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆139Updated 2 months ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆102Updated 2 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆408Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,203Updated 2 weeks ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆128Updated 3 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,609Updated last year
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆151Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆300Updated 9 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆285Updated 3 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆130Updated 8 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆776Updated 6 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆575Updated 7 months ago
• WangXuan95 / USTC-RVSoC
  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
  ☆377Updated last year
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆710Updated last year
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆343Updated last year
• alexforencich / verilog-uart
  Verilog UART
  ☆445Updated last year
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆903Updated last month
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆89Updated 8 months ago
• xupsh / pp4fpgas-cn-hls
  HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
  ☆235Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆186Updated last year