SUAT-lhy / MEISHAV100---FPGA-verification-on-VC707View external linksLinks
The MEISHA V100 contains four 64-bit RISC-V RV64GC，a 5-stage in-order scalar pipeline, comprehensive peripherals and interfaces. The system architecture is designed for flexibility, performance, and easy verification on FPGA platforms. The MEISHA V100 FPGA User Guide provides comprehensiv
☆18Feb 2, 2026Updated 2 weeks ago
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