eldrickm / wakey_wakey
EE 272B - VLSI Design Project
☆11Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for wakey_wakey
- Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…☆12Updated 4 years ago
- LSTM neural network (verilog)☆11Updated 5 years ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 2 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆10Updated last year
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆29Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- CNN Accelerator in Frequency Domain☆10Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- MulApprox - A comprehensive library of state-of-the-art approximate multipliers☆20Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆29Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆20Updated last year
- ☆26Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆24Updated 3 years ago
- tpu-systolic-array-weight-stationary☆18Updated 3 years ago
- ☆12Updated 10 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆23Updated 5 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆14Updated last year
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆33Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆54Updated 3 months ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆32Updated 2 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆12Updated 4 months ago