eldrickm / wakey_wakey
EE 272B - VLSI Design Project
☆11Updated 3 years ago
Alternatives and similar repositories for wakey_wakey
Users that are interested in wakey_wakey are comparing it to the libraries listed below
Sorting:
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- LSTM neural network (verilog)☆13Updated 6 years ago
- Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…☆12Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆18Updated last year
- DMA controller for CNN accelerator☆13Updated 7 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆31Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- ☆27Updated 5 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆14Updated 8 months ago
- ☆9Updated 4 years ago
- ☆33Updated 6 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆8Updated last year
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Updated 5 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Template for project1 TPU☆18Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago