ChFrenkel / tinyODINLinks
tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.
☆75Updated 2 years ago
Alternatives and similar repositories for tinyODIN
Users that are interested in tinyODIN are comparing it to the libraries listed below
Sorting:
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆215Updated 6 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 9 months ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆92Updated 3 years ago
- ☆30Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Updated 4 years ago
- Spiking Neural Network RTL Implementation☆64Updated 4 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- A repository FPGA-friendly SNN models☆35Updated 4 years ago
- Fully opensource spiking neural network accelerator☆163Updated 2 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆19Updated 5 years ago
- ☆53Updated last year
- ☆20Updated 4 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Updated 5 years ago
- FPGA Design of a Spiking Neural Network.☆45Updated last year
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆40Updated 5 years ago
- ☆17Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 2 years ago
- ☆98Updated 5 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆27Updated 6 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆14Updated 2 years ago
- Framework for radix encoded SNN on FPGA☆18Updated 4 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆63Updated last year
- SNN on FPGA☆11Updated 3 years ago
- ☆19Updated 2 months ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last month
- FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch☆98Updated 3 weeks ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆37Updated 7 years ago