NikhilMukraj / spiking-neural-networks-hardwareLinks
An FPGA design for simulating biological neurons
☆14Updated 11 months ago
Alternatives and similar repositories for spiking-neural-networks-hardware
Users that are interested in spiking-neural-networks-hardware are comparing it to the libraries listed below
Sorting:
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Updated last year
- The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"☆11Updated last year
- ☆28Updated 4 years ago
- Basic floating-point components for RISC-V processors☆10Updated 7 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- Motion Estimation implementation by using Verilog HDL☆12Updated 11 months ago
- sram/rram/mram.. compiler☆35Updated last year
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆38Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆17Updated 5 years ago
- ☆14Updated 2 years ago
- EE 272B - VLSI Design Project☆12Updated 3 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆20Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 3 weeks ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- LSTM neural network (verilog)☆13Updated 6 years ago
- Matrix multiplication accelerator on ZYNQ SoC.☆9Updated last month
- Template for project1 TPU☆18Updated 4 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆34Updated 7 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 4 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- Digital Standard Cells based SAR ADC☆14Updated 3 years ago
- ☆27Updated 5 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆56Updated 2 years ago