NikhilMukraj / spiking-neural-networks-hardware
An FPGA design for simulating biological neurons
☆13Updated 6 months ago
Alternatives and similar repositories for spiking-neural-networks-hardware:
Users that are interested in spiking-neural-networks-hardware are comparing it to the libraries listed below
- ☆12Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆13Updated 11 months ago
- ☆25Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated 3 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆9Updated last year
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- LSTM neural network (verilog)☆13Updated 6 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆12Updated last year
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆14Updated 5 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 6 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆26Updated 3 months ago
- ☆27Updated 9 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- ☆24Updated 5 years ago
- ☆26Updated 5 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆32Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 2 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆49Updated last year
- Neural Network accelerator powered by MVUs and RISC-V.☆12Updated 6 months ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆22Updated 5 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- ☆11Updated last week
- A Spiking Neuron Network Project in Verilog Implementation☆20Updated 6 years ago