Alternatives and similar repositories for riscv-baremetal-DefaultConfig:

Users that are interested in riscv-baremetal-DefaultConfig are comparing it to the libraries listed below

• ucb-art / fft
  ☆21Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆84Updated 4 months ago
• sifive / block-nvdla-sifive
  ☆42Updated 3 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 5 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 6 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆61Updated 5 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 7 months ago
• chipsalliance / uvm-verilator
  ☆82Updated last year
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 10 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆68Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆64Updated 5 years ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆17Updated last month
• hdlguy / zcu104_ubuntu
  A project to demonstrate Xilinx MPSOC running Ubuntu
  ☆20Updated last month
• oprecomp / DDR4_controller
  ☆50Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆156Updated this week
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆130Updated last month
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆69Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• SpinalHDL / VexRiscvSocSoftware
  ☆26Updated 3 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆99Updated 6 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆53Updated last week
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆64Updated 2 years ago