Alternatives and similar repositories for TinyTS

Users that are interested in TinyTS are comparing it to the libraries listed below

• harvard-acc / EdgeBERT
  HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
  ☆54Updated last year
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆33Updated 2 years ago
• union-codesign / union
  ☆14Updated 4 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆62Updated 3 months ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆42Updated 6 years ago
• suchandler96 / gem5-NVDLA
  ☆42Updated 10 months ago
• maestro-project / frame
  FRAME: Fast Roofline Analytical Modeling and Estimation
  ☆39Updated 2 years ago
• microideax / T-DLA
  ☆19Updated 6 years ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆88Updated 2 years ago
• NaelF / BinaryCoP
  Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices
  ☆12Updated 4 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆48Updated last month
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆21Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆61Updated 4 years ago
• CLab-HKUST-GZ / micro58-axcore
  ☆30Updated 3 months ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆28Updated last year
• uiuc-arc / felix
  Optimize tensor program fast with Felix, a gradient descent autotuner.
  ☆30Updated last year
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆185Updated 3 weeks ago
• lixiuhong / batched_gemm
  ☆40Updated 5 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆39Updated 5 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 3 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆46Updated 3 years ago
• SET-Scheduling-Project / SoMa-HPCA2025
  ☆26Updated 11 months ago
• pku-liang / TileFlow
  TileFlow is a performance analysis tool based on Timeloop for fusion dataflows
  ☆66Updated last year
• pku-liang / AMOS
  Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators
  ☆121Updated 3 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆33Updated last year
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆43Updated 2 years ago
• gty111 / SimpleUseGpgpuSim
  GPGPU-SIM 使用篇
  ☆14Updated 3 years ago