mit-emze / raella
☆9Updated last year
Alternatives and similar repositories for raella:
Users that are interested in raella are comparing it to the libraries listed below
- HW accelerator mapping optimization framework for in-memory computing☆22Updated 2 months ago
- ☆9Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆21Updated 3 years ago
- ☆25Updated 11 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated last week
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- ☆16Updated 11 months ago
- A general framework for optimizing DNN dataflow on systolic array☆34Updated 4 years ago
- ☆53Updated 3 weeks ago
- ☆39Updated 9 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆20Updated 9 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- MNSIM version 1.1. We have uploaded a high-level modeling tool and please use this version: https://github.com/Zhu-Zhenhua/MNSIM_Python☆12Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆61Updated 3 weeks ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆50Updated last month
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆38Updated 5 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆16Updated 7 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆8Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆51Updated 3 weeks ago
- A bit-level sparsity-awared multiply-accumulate process element.☆14Updated 8 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆11Updated 2 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆29Updated 10 months ago
- A Fast DNN Accelerator Design Space Exploration Framework.☆46Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- ☆33Updated 3 years ago