Alternatives and similar repositories for legoHDL

Users that are interested in legoHDL are comparing it to the libraries listed below

• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 7 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆49Updated this week
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆32Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 7 months ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 2 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated 2 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆25Updated 6 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated 2 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 7 months ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated last week
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆135Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆153Updated last week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆35Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated last week
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆35Updated 10 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆35Updated last month
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 11 months ago
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆108Updated 2 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• eine / hwd-ide
  ☆20Updated 5 years ago