mrisc32 / mc1
A computer (FPGA SoC) based on the MRISC32-A1 CPU
☆56Updated last year
Alternatives and similar repositories for mc1
Users that are interested in mc1 are comparing it to the libraries listed below
Sorting:
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- Reusable Verilog 2005 components for FPGA designs☆43Updated 2 months ago
- CMod-S6 SoC☆41Updated 7 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- MR1 formally verified RISC-V CPU☆55Updated 6 years ago
- SoftCPU/SoC engine-V☆54Updated last month
- Featherweight RISC-V implementation☆52Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- Miscellaneous ULX3S examples (advanced)☆77Updated 2 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- A CPU on an FPGA that you can play Zork on☆49Updated 8 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆59Updated 3 years ago
- Tools for FPGA development.☆45Updated 2 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆11Updated 6 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- A SoC for DOOM☆17Updated 4 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆22Updated 6 years ago
- Yosys Plugins☆21Updated 5 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- A Full Hardware Real-Time Ray-Tracer☆102Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆60Updated 5 months ago
- Experiments with Yosys cxxrtl backend☆48Updated 4 months ago
- UPduino☆27Updated 5 years ago