mrisc32 / mc1Links
A computer (FPGA SoC) based on the MRISC32-A1 CPU
☆54Updated 2 years ago
Alternatives and similar repositories for mc1
Users that are interested in mc1 are comparing it to the libraries listed below
Sorting:
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 7 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Tools for FPGA development.☆48Updated 2 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- A FPGA core for a simple SDRAM controller.☆123Updated 3 years ago
- Miscellaneous ULX3S examples (advanced)☆80Updated 3 months ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated 2 years ago
- A SoC for DOOM☆19Updated 4 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆44Updated 2 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆38Updated 3 years ago
- A simple GPU on a TinyFPGA BX☆81Updated 7 years ago
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- FPGA Odysseus with ULX3S☆68Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆94Updated 5 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆32Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 4 months ago
- CMod-S6 SoC☆42Updated 7 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆62Updated 6 years ago
- SoftCPU/SoC engine-V☆55Updated 6 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- PicoRV☆44Updated 5 years ago
- Doom classic port to lightweight RISC‑V☆97Updated 3 years ago
- mystorm sram test☆28Updated 8 years ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆28Updated 6 years ago
- UPduino☆27Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago