Alternatives and similar repositories for logLUTs

Users that are interested in logLUTs are comparing it to the libraries listed below

• tmeissner / gatemate_experiments
  Experiments with Cologne Chip's GateMate FPGA architecture
  ☆17Updated 2 years ago
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆34Updated 4 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆33Updated 9 months ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆44Updated 4 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆32Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆26Updated last month
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• rodrigomelo9 / verifying-foss-hdl-synthesizers
  a project to check the FOSS synthesizers against vendors EDA tools
  ☆12Updated 5 years ago
• esromneb / verilator-project-template
  Template Verilator project for beginners
  ☆13Updated 2 years ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆30Updated last week
• tomverbeure / fpga_quick_ram_update
  Quickly update a bitstream with new RAM contents
  ☆15Updated 4 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 6 years ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆46Updated last week
• juliancoy / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆15Updated 3 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆43Updated 9 months ago
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• skristiansson / wb_sdram_ctrl
  SDRAM controller with multiple wishbone slave ports
  ☆29Updated 7 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 4 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆58Updated 2 weeks ago
• hansfbaier / colorlight-qmtech-adapter
  Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor
  ☆19Updated 3 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 7 years ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆15Updated 5 years ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago