SymbioticEDA / MARLANN
Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
☆86Updated 5 years ago
Alternatives and similar repositories for MARLANN:
Users that are interested in MARLANN are comparing it to the libraries listed below
- Yet Another RISC-V Implementation☆86Updated 3 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆82Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 3 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆43Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- FuseSoC standard core library☆124Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆64Updated 9 months ago
- Mathematical Functions in Verilog☆86Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- ☆58Updated 3 years ago
- SpinalHDL Hardware Math Library☆82Updated 6 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- Extensible FPGA control platform☆55Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- ☆41Updated 4 years ago
- RISC-V Nox core☆62Updated 5 months ago
- Demo SoC for SiliconCompiler.☆56Updated this week
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Wishbone interconnect utilities☆38Updated 7 months ago
- Mutation Cover with Yosys (MCY)☆78Updated last month
- SoftCPU/SoC engine-V☆54Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆31Updated 3 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆134Updated last year
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 4 months ago