qiyancos / gem5-with-chinese-commentView external linksLinks
Gem5 with chinese comment and introduction (master) and some other std gem5 version.
☆42Jan 2, 2022Updated 4 years ago
Alternatives and similar repositories for gem5-with-chinese-comment
Users that are interested in gem5-with-chinese-comment are comparing it to the libraries listed below
Sorting:
- use two version gem5 to create spec2006 cpu simpoint & checkpoint☆16Oct 19, 2019Updated 6 years ago
- ☆22Nov 3, 2025Updated 3 months ago
- Implementing the Precise Runahead (HPCA'20) in gem5☆13Oct 5, 2023Updated 2 years ago
- ☆31Updated this week
- Sampled simulation of multi-threaded applications using LoopPoint methodology☆24Aug 3, 2025Updated 6 months ago
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆13Jun 7, 2025Updated 8 months ago
- MESIF cache coherency protocol for the GEM5 simulator☆15Jun 2, 2016Updated 9 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆14Sep 15, 2022Updated 3 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated 8 months ago
- gem5 configuration for intel's skylake micro-architecture☆53Jan 6, 2022Updated 4 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 2 months ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- RISC-V 64 CPU☆10Oct 4, 2025Updated 4 months ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- ☆64Dec 4, 2022Updated 3 years ago
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆81Jan 17, 2026Updated last month
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …☆669Feb 1, 2026Updated 2 weeks ago
- SYSU-ARCH is a LAB that focuses on the use and extending of simulators.☆10Dec 19, 2022Updated 3 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Automated test generator to detectcache side channel leakages.☆11Jul 1, 2019Updated 6 years ago
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated last year
- small and independent checkpoint☆12Nov 4, 2023Updated 2 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆256Oct 6, 2022Updated 3 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆20Jan 6, 2026Updated last month
- New Cache implementation using Gem5☆13Apr 2, 2014Updated 11 years ago
- ☆26Feb 27, 2025Updated 11 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Aug 29, 2023Updated 2 years ago
- Multiple approaches to statistical simulation for computer architects☆15Jun 1, 2020Updated 5 years ago
- About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.☆14Mar 1, 2023Updated 2 years ago
- ☆15Dec 15, 2022Updated 3 years ago
- ☆109Feb 12, 2024Updated 2 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 2 months ago
- a Computing In Memory emULATOR framework☆15May 19, 2024Updated last year
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- Code of "Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures", TCAD 2020☆13Apr 1, 2021Updated 4 years ago