Alternatives and similar repositories for FPGA_HW_Acceleration_Social_Disatancing_Monitor

Users that are interested in FPGA_HW_Acceleration_Social_Disatancing_Monitor are comparing it to the libraries listed below

• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆59Updated 5 years ago
• ptoupas / amd-open-hardware-23
  This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…
  ☆46Updated last year
• louisliuwei / pynq-dpu
  Migrate Xilinx edge AI solution to PYNQ
  ☆17Updated 4 years ago
• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆45Updated 6 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆106Updated 7 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆24Updated 3 years ago
• Xilinx / PYNQ_Bootcamp
  PYNQ Bootcamp 2019-2024 teaching materials.
  ☆48Updated 7 months ago
• zhutmost / edgeboard
  Make Baidu EdgeBoard Lite as a general Zynq FPGA development board
  ☆26Updated 2 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆152Updated 2 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆111Updated 5 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆35Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆90Updated 7 months ago
• Johnny-Zou / FPGA-Mnist
  Hand written number classification done in hardware (De1-SoC board) using neural networks
  ☆24Updated 7 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆46Updated 5 years ago
• jgoeders / dac_sdc_2022_designs
  ☆17Updated 2 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• amiq-consulting / image-upscaling-CNN
  How to Accelerate an Image Upscaling CNN on FPGA Using HLS
  ☆23Updated 3 years ago
• xupsh / 2019_SummerCamp
  2019 SEU-Xilinx Summer School
  ☆49Updated 6 years ago
• lllibano / LABFT
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…
  ☆15Updated last year
• Xilinx / kria-vitis-platforms
  Kria Vitis platforms and overlays
  ☆103Updated 2 months ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• shin-yamashita / 6th-AI-Edge-Contest
  RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.
  ☆13Updated 2 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆105Updated 2 years ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆108Updated 6 years ago
• sfox14 / pynq-ekf
  A multi-board Extended Kalman Filter (EKF)
  ☆31Updated 6 years ago