Alternatives and similar repositories for mycpu

Users that are interested in mycpu are comparing it to the libraries listed below

• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆83Updated 2 years ago
• Invalid-Syntax-NSCSCC / invalid-cpu
  CPU source code for NSCSCC 2023
  ☆15Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 10 months ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 5 months ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆143Updated last year
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆29Updated last year
• iFuProcessor / iFuCore
  ☆20Updated last year
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated last year
• MaZirui2001 / Zircon
  ☆30Updated 7 months ago
• puckbee / moli
  ☆29Updated last month
• MrAMS / Nagi
  CPU敏捷开发框架（龙芯杯2024）
  ☆25Updated last year
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• OpenXiangShan / gsim
  ☆53Updated last week
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆51Updated 4 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 5 years ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆23Updated 10 months ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆117Updated 10 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 6 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆179Updated 11 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆30Updated this week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆153Updated this week
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 5 months ago
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Out-of-order CPU design from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品
  ☆20Updated last year
• OSCPU / chisel-playground
  ☆67Updated 7 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 4 months ago