briansune / USB-PD-3.1-VerilogLinks
USB-PD-3.1-Verilog
☆15Updated last year
Alternatives and similar repositories for USB-PD-3.1-Verilog
Users that are interested in USB-PD-3.1-Verilog are comparing it to the libraries listed below
Sorting:
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- Testbenches for HDL projects☆19Updated this week
- SPI-Flash XIP Interface (Verilog)☆40Updated 3 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- USB Type-C Power Delivery FPGA☆24Updated 2 years ago
- hdmi-ts Project☆13Updated 8 years ago
- FT2232HL JTAG & UART Downloader☆19Updated 4 years ago
- USB serial device (CDC-ACM)☆40Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆19Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- ☆30Updated 8 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 4 months ago
- USB 1.1 PHY☆11Updated 11 years ago
- VHDL PCIe Transceiver☆29Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆18Updated 2 years ago
- Delta Sigma DAC FPGA☆43Updated 5 months ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 6 years ago
- Small footprint and configurable JESD204B core☆45Updated 2 months ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- Digital FM Radio Receiver for FPGA☆61Updated 9 years ago
- IEEE P1735 decryptor for VHDL☆35Updated 10 years ago
- development interface mil-std-1553b for system on chip☆22Updated 7 years ago
- Time to Digital Converter (TDC)☆31Updated 4 years ago
- SDIO Device Verilog Core☆22Updated 7 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆71Updated 3 years ago