briansune / USB-PD-3.1-VerilogLinks
USB-PD-3.1-Verilog
☆17Updated last year
Alternatives and similar repositories for USB-PD-3.1-Verilog
Users that are interested in USB-PD-3.1-Verilog are comparing it to the libraries listed below
Sorting:
- USB Full Speed PHY☆48Updated 5 years ago
- Testbenches for HDL projects☆22Updated last week
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- USB 1.1 PHY☆11Updated 11 years ago
- USB Type-C Power Delivery FPGA☆27Updated 3 years ago
- hdmi-ts Project☆13Updated 8 years ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- IEEE P1735 decryptor for VHDL☆39Updated 10 years ago
- ULPI Link Wrapper (USB Phy Interface)☆34Updated 5 years ago
- FT2232HL JTAG & UART Downloader☆20Updated 4 years ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆31Updated 4 years ago
- USB serial device (CDC-ACM)☆43Updated 5 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 months ago
- ☆30Updated 8 years ago
- Basic USB-CDC device core (Verilog)☆85Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Updated 11 months ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 4 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆18Updated 7 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- ☆36Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Computational Storage Device based on the open source project OpenSSD.☆29Updated 5 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆20Updated 2 years ago
- ☆16Updated 6 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆86Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Updated 7 years ago