briansune / USB-PD-3.1-VerilogLinks
USB-PD-3.1-Verilog
☆15Updated last year
Alternatives and similar repositories for USB-PD-3.1-Verilog
Users that are interested in USB-PD-3.1-Verilog are comparing it to the libraries listed below
Sorting:
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- Testbenches for HDL projects☆20Updated last week
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- USB Type-C Power Delivery FPGA☆24Updated 3 years ago
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- FT2232HL JTAG & UART Downloader☆19Updated 4 years ago
- ☆30Updated 8 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆19Updated 2 years ago
- USB 1.1 PHY☆11Updated 11 years ago
- ULPI Link Wrapper (USB Phy Interface)☆29Updated 5 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Updated 7 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 8 months ago
- IEEE P1735 decryptor for VHDL☆36Updated 10 years ago
- hdmi-ts Project☆13Updated 8 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆21Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- VHDL PCIe Transceiver☆30Updated 5 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 6 months ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Digilent JTAG clone hardware + eeprom firmware (.bin)☆67Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 8 months ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- USB 2.0 Device IP Core☆69Updated 8 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago