briansune / USB-PD-3.1-Verilog
USB-PD-3.1-Verilog
☆14Updated last year
Alternatives and similar repositories for USB-PD-3.1-Verilog
Users that are interested in USB-PD-3.1-Verilog are comparing it to the libraries listed below
Sorting:
- USB Type-C Power Delivery FPGA☆22Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆26Updated 5 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Testbenches for HDL projects☆16Updated this week
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆17Updated 2 years ago
- USB 1.1 PHY☆11Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated last month
- USB serial device (CDC-ACM)☆38Updated 4 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Updated 3 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆19Updated 3 months ago
- IEEE P1735 decryptor for VHDL☆32Updated 9 years ago
- FPGA board-level debugging and reverse-engineering tool☆37Updated 2 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆28Updated 8 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆12Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 years ago
- ☆45Updated 2 years ago
- USB capture IP☆21Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- ☆31Updated this week
- VHDL PCIe Transceiver☆28Updated 4 years ago
- ☆30Updated 8 years ago
- Computational Storage Device based on the open source project OpenSSD.☆23Updated 4 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆45Updated 3 years ago