Alternatives and similar repositories for RMM4NC30F2X:

Users that are interested in RMM4NC30F2X are comparing it to the libraries listed below

• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 5 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OSCPU / chisel-playground
  ☆64Updated 2 months ago
• xunqianxun / liguoqi-rv64-cpu
  RISC-V 64 CPU
  ☆10Updated 2 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆32Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 10 months ago
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆18Updated 5 months ago
• MrAMS / Nagi
  基于difftest改进的CPU敏捷开发框架（龙芯杯2024）
  ☆13Updated 7 months ago
• MaZirui2001 / Zircon
  ☆25Updated 2 months ago
• OSCPU / ysyxSoC
  ☆85Updated 2 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated 9 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated last year
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆11Updated 4 months ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• OSCPU / yosys-sta
  ☆62Updated last week
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated last year
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• sequencer / arithmetic
  ☆32Updated 3 weeks ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆19Updated 3 weeks ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆78Updated last year
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 9 months ago
• CherrySprings / CherrySprings
  ☆18Updated last year
• BriMonzZY / multi-mode-fft-processor
  R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
  ☆11Updated last month
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• jaypiper / simulator
  ☆27Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆65Updated 8 months ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆63Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆44Updated last week