RISMicroDevices / RMM4NC30F2XLinks
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
☆11Updated 3 years ago
Alternatives and similar repositories for RMM4NC30F2X
Users that are interested in RMM4NC30F2X are comparing it to the libraries listed below
Sorting:
- ☆33Updated 7 months ago
- The 'missing header' for Chisel☆21Updated 7 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆27Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 weeks ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated last month
- Hardware design with Chisel☆35Updated 2 years ago
- This is an IDE for YSYX_NPC debuging☆12Updated 10 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆43Updated last year
- RV64GC Linux Capable RISC-V Core☆40Updated last week
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- ☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- ☆18Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 9 months ago
- ☆67Updated 8 months ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆15Updated 3 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 3 years ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆44Updated 3 weeks ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- RISC-V 64 CPU☆10Updated 3 weeks ago
- ☆62Updated 3 weeks ago
- ☆56Updated 6 years ago
- Advanced Architecture Labs with CVA6☆69Updated last year
- ☆30Updated 5 years ago
- A MCU implementation based PODES-M0O☆19Updated 5 years ago
- ☆30Updated last week