Alternatives and similar repositories for RMM4NC30F2X

Users that are interested in RMM4NC30F2X are comparing it to the libraries listed below

• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆23Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆33Updated last month
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 10 months ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last year
• xunqianxun / liguoqi-rv64-cpu
  RISC-V 64 CPU
  ☆10Updated 2 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆56Updated last year
• sequencer / arithmetic
  ☆33Updated 5 months ago
• OSCPU / chisel-playground
  ☆67Updated 7 months ago
• xjtuiair-cag / SiYuan
  A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
  ☆29Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated 9 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 10 months ago
• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆34Updated 2 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆21Updated 5 months ago
• BriMonzZY / multi-mode-fft-processor
  R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point
  ☆15Updated 2 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆67Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆15Updated last year
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆14Updated 4 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆30Updated 5 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆20Updated 4 months ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆40Updated last week
• OSCPU / ysyxSoC
  ☆86Updated last week
• pulp-platform / axi_llc
  ☆29Updated 3 weeks ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆65Updated 3 years ago