Alternatives and similar repositories for RV64emu-rs:

Users that are interested in RV64emu-rs are comparing it to the libraries listed below

• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆78Updated last week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆60Updated 3 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆38Updated this week
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated last year
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 8 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆87Updated 6 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated 2 weeks ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆96Updated 4 months ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆17Updated 4 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆35Updated last year
• chili-chips-ba / wireguard-fpga
  Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…
  ☆74Updated this week
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆29Updated 10 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 4 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 4 months ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆50Updated 4 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆89Updated last week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• chipsalliance / tilelink
  ☆28Updated 3 months ago
• riscv / virtual-memory
  ☆36Updated 3 years ago
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆18Updated 7 months ago
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆48Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv / riscv-aia
  ☆86Updated 2 weeks ago
• riscv-non-isa / riscv-external-debug-security
  The RISC-V External Debug Security Specification
  ☆19Updated 2 weeks ago
• rustsbi / standalone
  Rapid prototyping and selection package for pure-Rust RISC-V firmware, with RustSBI + UEFI or RustSBI + LinuxBoot
  ☆27Updated 5 months ago
• yamak / axi-nodes
  ☆19Updated 3 years ago