Alternatives and similar repositories for RV64emu-rs

Users that are interested in RV64emu-rs are comparing it to the libraries listed below

• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆31Updated 3 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆82Updated last week
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated 2 months ago
• jiegec / jtag-remote-server
  Remote JTAG server for remote debugging
  ☆39Updated last year
• chipsalliance / chisel-nix
  Nix template for the chisel-based industrial designing flows.
  ☆42Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆72Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆42Updated 10 months ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆94Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated last month
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago
• plctlab / RISCV-Training
  Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.
  ☆34Updated last year
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆39Updated 3 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆118Updated 3 weeks ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆41Updated 4 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆36Updated this week
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆93Updated last month
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 6 months ago
• yamak / axi-nodes
  ☆19Updated 3 years ago
• chipsalliance / tilelink
  ☆30Updated 5 months ago
• riscv / riscv-aia
  ☆89Updated 2 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year