Alternatives and similar repositories for ICS-2021Spring-FDU

Users that are interested in ICS-2021Spring-FDU are comparing it to the libraries listed below

• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆44Updated 5 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 6 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆146Updated last year
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆135Updated 2 years ago
• iFuProcessor / iFuCore
  ☆20Updated last year
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆133Updated 5 years ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• MAdrid1011 / Zircon
  ☆29Updated 11 months ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆45Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• OpenXiangShan / XSAI
  A fork of Xiangshan for AI
  ☆35Updated this week
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆31Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 8 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆33Updated 6 years ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• cassuto / yamp-32
  NSCSCC 2020 - Yet Another MIPS Processor
  ☆14Updated 4 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 8 months ago
• OSCPU / yosys-sta
  ☆87Updated last month
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆180Updated 4 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆27Updated 7 years ago
• gilgamsh / GenshinCPU
  Our repository for NSCSCC
  ☆19Updated 10 months ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year