Alternatives and similar repositories for logic-synthesis

Users that are interested in logic-synthesis are comparing it to the libraries listed below

• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆54Updated this week
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆13Updated last year
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 5 years ago
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆131Updated 5 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆17Updated 2 years ago
• nbulsi / also
  A logic synthesis tool
  ☆73Updated last month
• davidkebo / verilog-parser
  A verilog parser
  ☆19Updated last year
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆98Updated 3 months ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 4 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆91Updated 3 years ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆22Updated 3 years ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆37Updated 6 months ago
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆145Updated 5 years ago
• pulp-platform / ELAU
  ☆18Updated 10 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 8 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆106Updated this week
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆58Updated last week
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆54Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆47Updated 4 months ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆80Updated last year
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆81Updated 2 weeks ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆42Updated last week
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆194Updated last year
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆83Updated 10 months ago